Browse Prior Art Database

Register Banking for IBM System/370

IP.com Disclosure Number: IPCOM000121747D
Original Publication Date: 1991-Sep-01
Included in the Prior Art Database: 2005-Apr-03
Document File: 2 page(s) / 64K

Publishing Venue

IBM

Related People

LiVecchi, PM: AUTHOR

Abstract

This article explores how the register banking concept found in several stack-based computer architectures could be applied to the IBM System/ 370* computer architecture. Disclosed is a method for reducing the instruction path length of handling interrupts in System 370 by implementing multiple banks, or sets, of registers, a way to indicate which bank is active and a method for manipulating information in the inactive register banks.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Register Banking for IBM System/370

      This article explores how the register banking concept
found in several stack-based computer architectures could be applied
to the IBM System/ 370* computer architecture. Disclosed is a method
for reducing the instruction path length of handling interrupts in
System 370 by implementing multiple banks, or sets, of registers, a
way to indicate which bank is active and a method for manipulating
information in the inactive register banks.

      Processor interrupts on System 370 cause the current PSW to be
stored and a new PSW loaded, thus switching processing to the
appropriate interrupt handling routine. These routines are
responsible for storing the contents of the system's registers in
memory so that the interrupted program may be resumed following
interruption handling. Following this, these routines must
reestablish addressability to their own key work areas and control
blocks.  At the completion of interrupt handling, a scheduler is
often used to select from a list of recently interrupted programs,
the one which should regain control. The saved registers and PSW are
reloaded and processing continues.

      Register banking avoids the need to store and retrieve the
interrupted program's registers in memory and the need to reestablish
addressability in the interrupt handling routine.  One set of
registers is allocated to the current program.  Another is allocated
to the interrupt handlers. An indicator is stored in the PSW as to
which register bank is currently in use.  Wh...