Browse Prior Art Database

IBM PC Interface Integrated Circuit

IP.com Disclosure Number: IPCOM000121749D
Original Publication Date: 1991-Sep-01
Included in the Prior Art Database: 2005-Apr-03
Document File: 4 page(s) / 126K

Publishing Venue

IBM

Related People

Gorga, KJ: AUTHOR

Abstract

The Personal Computer (PC) Interface Programmable Macro Logic Integrated Circuit (IC) is a device that allows the PC, PC XT*, or PC AT* Bus to connect with an Input/Output (I/O) adapter. The circuitry is programmed into a Signetics PLHS-501 Programmable Macro Logic IC. It is a 52-Pin PLCC case IC which can be programmed on an appropriate programmer by blowing internal fuse links. The chip is programmed to do an I/O address block decode, 3 channel Direct Memory Access selection and control, 4 interrupt level selection and control, and Data bus tranceiver control and handshaking.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

IBM PC Interface Integrated Circuit

      The Personal Computer (PC) Interface Programmable Macro
Logic Integrated Circuit (IC) is a device that allows the PC, PC XT*,
or PC AT* Bus to connect with an Input/Output (I/O) adapter.  The
circuitry is programmed into a Signetics PLHS-501 Programmable Macro
Logic IC.  It is a 52-Pin PLCC case IC which can be programmed on an
appropriate programmer by blowing internal fuse links.  The chip is
programmed to do an I/O address block decode, 3 channel Direct Memory
Access selection and control, 4 interrupt level selection and
control, and Data bus tranceiver control and handshaking.

      The I/O address block decoder section compares address A5-9
against an external set of switches or jumpers to decode a 32-address
block.  The switches or jumpers are compared against the PC Address
bus and are also qualified by the PC AEN line and an external input
Enable Host Interface.  The Enable Host Interface line is used to
externally disable the chip.  Three addresses are used for control on
the chip.  The two address lines used to decode the three addresses
are usually A0 and A1, but they could be connected to other address
lines.

      The DMA selection hardware uses an external set of 2 switches
or jumpers to determine which set of three DMA channels will be used.
The DMA Request line is tri-state enabled by the switches and DMA
Enable onto the PC bus.  DMA Enable allows for the enabling or
disabling of the DMA Request drivers by writing a 1 or 0 on data bus
DO (typically) to address XX2.  It is also reset by an external Power
On Reset (POR) signal.

      The Interrupt selection hardware uses an external set of 2
switches or jumpers to select 1 of 4 interrupt levels to use.  The
interrupt lines are tri-state enabled by the switches and Interrupt
Enable onto the PC bus.  Interrupt Enable is set or reset by writing
a 1 or 0 on data bus D1 (typically) to address XX2.  It is also
reset by an external POR signal.

      The Data Bus tranceiver and control hardware works in
conjunction with a 74HCT646 tranceiver/register IC.  This IC has a
separate input and output register in it.  A hardware handshaking is
used between the PC bus and the I/O Adapter. When an I/O write is
done by the PC bus side to the selected I/O address block of the
Interface chip (XX0 or XX1), a clock...