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High Security Logical Key Function for Computers

IP.com Disclosure Number: IPCOM000121758D
Original Publication Date: 1991-Sep-01
Included in the Prior Art Database: 2005-Apr-03
Document File: 5 page(s) / 192K

Publishing Venue

IBM

Related People

Abrahamsen, R: AUTHOR [+3]

Abstract

Described is a computer security implementation which is designed to provide a high degree of security through the use of logical key functions. The concept increases the security of data resident in a computer by requiring a user to provide a logical key to unlock the computer for use and renders the machine unusable and inoperable without proper authorization. In addition, the design provides a means of scrambling the failure analaysis code.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 48% of the total text.

High Security Logical Key Function for Computers

      Described is a computer security implementation which is
designed to provide a high degree of security through the use of
logical key functions.  The concept increases the security of data
resident in a computer by requiring a user to provide a logical key
to unlock the computer for use and renders the machine unusable and
inoperable without proper authorization.  In addition, the design
provides a means of scrambling the failure analaysis code.

      Typically, a lock bolted onto the frame of a computer has been
used as well as having a software lock to control power on self test
(POST) operations.  In addition, passwords are used to control
unauthorized usage.  Portable computers are particularly vulnerable
to stealing and need a method whereby accessibility is controlled.
As a result, the concept described herein provides a means whereby
additional protection is provided to add to the security of the
system.

      Generally, very large-system integration (VLSI) logic design
contains an amount of overhead, such that component testing and
manufacturing dictates the need for ever increased test coverage.
Toward this end, level-sensitive scan design (LSSD) logic has been
developed to enable the scanning in of known states to all latches
within the given part.  During board level testing, a known scan
vector is shifted into the scan latches just before the driver and
receiver (DR) circuits.  During this operation, the logic path to the
DR is ignored.  The vector is driven out to the next circuit chip and
received into the latches of the scan ring at that chip.  If the DRs
of both chips and the assembly is correct, then the vector driving
the first chip is the same vector that is received by the second
chip.

      Fuse elements are used in the DR circuits, such that the
blowing of either fuse causes a disruption in the DC power path.
Fig. 1 illustrates the use of the fuse as the point of comparison for
the driver enable input.  That is, the driver can function if and
only if the LSSD scan string bit correctly matches the programmed
state of the fuse. Once the driver is enabled, the delay of the
driver is unaffected.  Fig. 2 shows a second level block diagram
where there are normal driver input and output scan in and scan out
lines.

      Fig. 3 shows the DRs merged with the logic of the system.  If
the fuses and the scan vector match, then the normal operation of
each and every DR of the chip will function correctly.  However, if
any of the compares are faulted, then that driver or receiver will
not operate.  From a diagnostic point of view, a non-functioning
driver is hard to discriminate from a driver that should be in a
non-operating state.  Similarly, if a receiver is not working, it
would be almost impossible to tell.  This scrambling of the failure
analysis is important and moves the breaking of the chip's code up to
the level of only the best la...