Browse Prior Art Database

Array Command Module

IP.com Disclosure Number: IPCOM000121763D
Original Publication Date: 1991-Sep-01
Included in the Prior Art Database: 2005-Apr-03
Document File: 4 page(s) / 98K

Publishing Venue

IBM

Related People

Dieffenderfer, JN: AUTHOR [+3]

Abstract

A SIMD (Single Instruction Multiple Data stream) instruction bus provides efficient interprocessor communication among one master and ten slave processors.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Array Command Module

      A SIMD (Single Instruction Multiple Data stream)
instruction bus provides efficient interprocessor communication among
one master and ten slave processors.

      Referring to Fig. 1, control unit (CU) broadcasts instructions
to the processing elements (PEs).  The PEs then execute the
instructions in lock-step fashion.  The CU has the ability to mask
off individual PEs when they are not needed for particular
operations.  The PEs report status (operation results, diagnostics,
errors, etc.) via an interprocessor communications bus (not shown).

      An array command PE (see Fig. 2) includes: a System Interface
Module (SIM), a Device Interface Module (DIM), a Microprocessor (MP),
a Control Store (CS), and an Array Command (Slave) SIMD instruction
bus and interprocessor communications module.  The CU includes an
Array Command (Master) SIMD instruction bus and interprocessor
communications module.

      When the CU receives an operation request from the host, its
microprocessor converts the request into a sequence of PE
instructions.  The instructions are placed in CU control store.
Using Direct Memory Access the CU Array Command (Master) reads CU
control store and transmits the PE instructions across the SIMD
instruction bus.  Data is streamed across the bus in a burst, along
with two data strobes.  The data strobes are the L1/L2 clocks for the
receiving LSSD (Level-Sensitive Scan Design) logic in the PE Array
Command (Slave).  (See EDS Manual 3531 LSSD Design Techniques R90 for
a description of LSSD and L1/L2 clocks.) In this manner, the CU Array
Command (Master) remotely controls the PE Array Command (Slave) logic
such that synchronization controls are not needed during the
transfer.  The PE Array Command (Slave) receives the instruction
stream, then transfers it into PE control store.

      The CU has the ability to selectively mask of...