Browse Prior Art Database

Data Combining for Cache Accesses

IP.com Disclosure Number: IPCOM000121765D
Original Publication Date: 1991-Sep-01
Included in the Prior Art Database: 2005-Apr-03
Document File: 2 page(s) / 82K

Publishing Venue

IBM

Related People

Liu, L: AUTHOR

Abstract

Disclosed are techniques for optimizing performance of caches by offering the capability of satisfying multiple cache requests through a single access to the arrays.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Data Combining for Cache Accesses

      Disclosed are techniques for optimizing performance of
caches by offering the capability of satisfying multiple cache
requests through a single access to the arrays.

      Cache access is normally achieved at certain granule. Multiple
accesses to the cache may often be delayed due to conflict on the
array ports.  For instance, for a cache design with quadword
interleaved array(s), 2 accesses to the same interleave port cannot
be satisfied concurrently unless more expensive (e.g., multi-ported)
array design is used. From trace analysis we observe that successive
memory accesses (e.g., operand fetches) hit the same unit with
observable frequencies.  Such likelihood increases as the granule
becomes larger.  In this invention we take advantage of such
observation and provide simple techniques for improving performance
of multiple accesses without requiring special technology support on
arrays.

      The basic idea is to combine the handling of multiple cache
accesses through a single array access when they hit the same access
unit.  The techniques will be illustrated using an example.

      Consider a cache with arrays 4-way interleaved at quadword (16
byte) granule.  Each interleave bank can support only 1 array access
(fetch or store) per cycle. Assume that, at an interleave bank, 2
fetches (X and Y) are pending at a certain point.  There are two
possibilities:
1.   X and Y belong to different quadwords  -  In this case data
accesses cannot be satisfied for both of X and Y in the same cycle.
2.   X and Y belong to the same quadword  -  In this case both
accesses can be satisfied through a single quadword read from the
cache array(s) though proper data shifting may be needed for each of
the accesses.

      Whether X and Y are hitting identical quadword can clearly be
determined in a variety of ways.  One possibility is for their
addresses to be compared in an earlier cycle. A more aggressive
approach is to have their addresses compared (with each other) while
the ar...