Browse Prior Art Database

Dual Control Block I/O Controller

IP.com Disclosure Number: IPCOM000121766D
Original Publication Date: 1991-Sep-01
Included in the Prior Art Database: 2005-Apr-03
Document File: 2 page(s) / 66K

Publishing Venue

IBM

Related People

Dieffenderfer, JN: AUTHOR [+3]

Abstract

Microcode interrupt service time and strict hardware/microcode synchronization can be eliminated in I/O controllers by managing the system and device interface transfers with linked operation control blocks.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 60% of the total text.

Dual Control Block I/O Controller

      Microcode interrupt service time and strict
hardware/microcode synchronization can be eliminated in I/O
controllers by managing the system and device interface transfers
with linked operation control blocks.

      The figure represents an I/O controller with a system interface
module and a device interface module.  Each has the ability to fetch
an operation control block from control store.  The control store is
partitioned such that microcode shares its memory space with the
operation control blocks.

      The data transfer operations on each interface are processed as
follows.
1.   The interface module initiates an operation using the HEAD next
pointer to fetch the next operation control block from the request
queue.  This sequence initiates the operation using the transfer
control information when there is a valid request, signified by the
Valid Flag.  If there is no valid request, signified by the Invalid
Flag, the interface module terminates the control block fetch without
overlaying the HEAD next pointer, then pauses waiting for a signal
from the microcode that the operation control block list is not
empty.
2.   The hardware performs the operation as described in the transfer
control information.
3.   After the operation completes, the interface module posts an
interrupt to the microcode and initiates the next operation using the
new next pointer as described above in step 1.  The interrupt is
handled co...