Browse Prior Art Database

Asynchronous Bus Controller

IP.com Disclosure Number: IPCOM000121769D
Original Publication Date: 1991-Sep-01
Included in the Prior Art Database: 2005-Apr-03
Document File: 4 page(s) / 98K

Publishing Venue

IBM

Related People

Dieffenderfer, JN: AUTHOR [+3]

Abstract

Specific wait states for various devices sharing the Motorola 68020 bus are dynamically provided by an asynchronous state machine that monitors the progress of the 68020 bus cycle and provides programmable wait states.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Asynchronous Bus Controller

      Specific wait states for various devices sharing the
Motorola 68020 bus are dynamically provided by an asynchronous state
machine that monitors the progress of the 68020 bus cycle and
provides programmable wait states.

      The block diagram of Fig. 1 shows four major functional
elements of the 68020 bus controller.
      o    Device selection is performed by the Address Decoder block
(DECODE).  Upper order address bits validated by Micro_AS are decoded
along with some control signals to ensure that the 68020 is not
operating in CPU space.
      o    The Wait State Select Register is a memory mapped register
in the bus controller which is programmable by the 68020 and is used
to choose the desired wait states for each device selection. This
register has a wait state select field for each device on the bus.
      o    The S-State detector is an asynchronous state machine that
tracks the current S-State of the microprocessor.  It is shown in
more detail in Fig. 2.
      o    The DSACKx generation block decodes the signals provided
by the other three functional blocks to activate DSACKx to terminate
the bus cycle with the desired amount of wait states.

      The S-State detector as an asynchronous self-clearing timing
ring.  Each of the LSSD (Level-Sensitive Scan Design) latches shown
has both L1 and L2 clocks tied active permitting the set and reset
action to occur asynchronously. The NAS_DET latch is set whenever
Micro_AS is deasserted marking the end of the cycle.  The next cycle
begins when Micro_AS is asserted again.  The first positive Micro_CK
in a cycle is the S2 state.  Once...