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Browse Prior Art Database

CPU Bus Bandwidth Pacing in a Dual Bus System

IP.com Disclosure Number: IPCOM000121785D
Original Publication Date: 1991-Sep-01
Included in the Prior Art Database: 2005-Apr-03
Document File: 2 page(s) / 50K

Publishing Venue

IBM

Related People

Aldereguia, A: AUTHOR [+3]

Abstract

This article describes a technique and hardware implementation which enhances a dual-bus system bus bandwidth allocation by utilizing three timers to efficiently manage CPU access to the bus.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 85% of the total text.

CPU Bus Bandwidth Pacing in a Dual Bus System

      This article describes a technique and hardware
implementation which enhances a dual-bus system bus bandwidth
allocation by utilizing three timers to efficiently manage CPU access
to the bus.

      The dual-bus architecture system allows the CPU and bus masters
to share memory access.  Previous implementations of the bus
bandwidth allocation method used consecutive cache hit cycles to
indicate that the CPU no longer needed the system bus.  Because the
CPU can now share system memory access with a bus master, the bus can
be returned to a master when the CPU is accessing system memory as
well as cache.  Fig. 1 is a timing diagram showing bus utilization
where the CPU owns the system bus during memory accesses.

      The dual-bus bandwidth allocation method is implemented in the
Zimmer memory controller by three programmable timers.  Fig. 2 shows
bus utilization where the bus master owns the system bus and the CPU
shares system memory.  When a bus master is using the system bus and
the CPU requires a system bus cycle, a timer is started that
determines how long the CPU will wait for the master to relinquish
the bus prior to the CPU preempting for the bus.  Once the CPU has
preempted and been granted the bus, a second timer starts that
determines how long the CPU will hold the system bus. A third timer
(system bus idle timer) is used to detect no CPU activity on the
system bus.  When the system bus idle ti...