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Browse Prior Art Database

Analog PLL With Quick Phase Lock

IP.com Disclosure Number: IPCOM000121786D
Original Publication Date: 1991-Sep-01
Included in the Prior Art Database: 2005-Apr-03
Document File: 6 page(s) / 221K

Publishing Venue

IBM

Related People

Coburn, R: AUTHOR [+3]

Abstract

Disclosed is an analog PLL that provides minimum phase error lock without requiring a preamble. The circuit is a hybrid digital and analog implementation that combines the low jitter of an analog PLL and the fast lock of a digital PLL.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 36% of the total text.

Analog PLL With Quick Phase Lock

      Disclosed is an analog PLL that provides minimum phase
error lock without requiring a preamble.  The circuit is a hybrid
digital and analog implementation that combines the low jitter of an
analog PLL and the fast lock of a digital PLL.

      Past approaches to solving the problem of phase-locking to
burst- mode data has been to either significantly increase the
bandwidth of the PLL or use a long sequence of start-up bits.
Increasing the band width of the PLL is undesirable because this
causes instability and increases the noise sensitivity. Lengthening
the start-up sequence is also undesirable because this decreases the
effective bit rate since the time to phase-lock can be quite long
compared to the bit times if a relatively narrow-band PLL is used.

      The scheme used in this disclosure utilizes a narrow bandwidth
PLL with digital logic to quickly phase-lock. Just one data bit is
required to phase-lock but more are used to reduce noise
susceptibility.  The digital logic continuously monitors the incoming
data.  If N valid bits are received within the time-out limit, the
delay stage of the VCO closest to having the proper phase
relationship is selected.  The delay of each individual VCO stage
determines the granularity of the phase- lock.  As more delay stages
are added and the delay of each stage decreases, the closer the
selected phase will be to the ideal phase (with respect to the data).

      Fig. 1 shows a block diagram of the disclosure which
illustrates the general concepts involved.  The Quick Phase-Lock PLL
is composed of two major parts.  The first part is a normal PLL which
uses both a Phase Detector (PD) and a Frequency Detector (FD).  The
FD is used to lock the PLL to the operating frequency, while the PD
locks the PLL to the proper phase relationship of the data.  The PLL
also has an M-stage ring oscillator as the VCO.

      The second part of the disclosure is the Digital Decision
Logic.  This consists of a state machine and seven logical macros.
The seven macros and a brief description of each follows:
      1) Bit Counter - Counts the number of valid data bits. N valid
bits must be received before PD mode is selected.
 2) Bit Timer - Starts timing at the first valid data bit.  Resets
the Bit Counter if N valid bits are not received before it times out.
This prevents random noise pulses from eventually switching the PLL
into PD mode.
      3) Data Valid - Determines a valid data bit from the received
data bit stream.
      4) Idle Detector - Detects an idle condition on the data line.
If data stop, this macro puts the PLL back into FD mode.
 5) Stage Follower - Continuously monitors the state of the Ring
Oscillator and separately latches its state on the leading edge of
each data bit.
      6) Combinatorial - A simply 'AND-OR' network which selects the
proper Ring Oscillator stage that aligns with the leading edge of
received...