Browse Prior Art Database

Parallel Segment Adder

IP.com Disclosure Number: IPCOM000121809D
Original Publication Date: 1991-Sep-01
Included in the Prior Art Database: 2005-Apr-03
Document File: 1 page(s) / 56K

Publishing Venue

IBM

Related People

Hilker, SA: AUTHOR [+2]

Abstract

Disclosed is an invention which divides a HW binary adder into segments; each segment can be treated as a narrower adder independent of the other segments.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 62% of the total text.

Parallel Segment Adder

      Disclosed is an invention which divides a HW binary adder into
segments; each segment can be treated as a narrower adder independent
of the other segments.

      This invention assumes the carry-in to a specific segment of
the adder will not affect the carry-out of that segment, thereby
reducing the length of the total carry propagation.

      There are four possible combinations when adding two bits
together.  For two of these combinations the carry-in affects the
value of the carry-out; that is when one and only one of the two bits
is a '1'.  For the other two combinations a carry-out is generated
(carry-out=1) or killed (carry-out=0).  If this idea is expanded to 8
bits, the probability that a carry-in affects the carry-out is
(1/2)**8 or 1/256 assuming random data.

      Two pieces of logic are required for each segment of the adder:
the carry logic and the sum logic.  Each segment's carry and sum
logic are independent.  The carry logic sends the carryout to the
more significant segment's sum logic.  The sum logic provides the sum
outputs given the lesser significant segment's carry-out.  The wider
the segment, the less likely the carry-in will affect the carry-out.

      Detection of the case where the carry-in to a segment does
affect the carry-out, can be accomplished in parallel with the sum
and carry logic.  If this occurs, then the sum has to be corrected
for each segment where the lesser significant seg...