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Self Test for Growable Arrays

IP.com Disclosure Number: IPCOM000121810D
Original Publication Date: 1991-Sep-01
Included in the Prior Art Database: 2005-Apr-03
Document File: 1 page(s) / 64K

Publishing Venue

IBM

Related People

Aipperspach, AG: AUTHOR [+4]

Abstract

The following information introduces the use of a reconfigurable self-test macro integrated into a growable 1-port static SRAM subsystem. The self-test engine will generate the address and data vectors necessary to perform a comprehensive deterministic test on any configured SRAM macro. The organization of the storage array is arranged so a common set of circuits can be used for the self-test engine independent of the address space, data width, or number of storage lines multiplexed together to form one external data bit.

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Self Test for Growable Arrays

      The following information introduces the use of a
reconfigurable self-test macro integrated into a growable 1-port
static SRAM subsystem.  The self-test engine will generate the
address and data vectors necessary to perform a comprehensive
deterministic test on any configured SRAM macro.  The organization of
the storage array is arranged so a common set of circuits can be used
for the self-test engine independent of the address space, data
width, or number of storage lines multiplexed together to form one
external data bit.

      The self-test engine contains a main controller, a data pattern
generator, a programmable up/down counter, and the logic necessary to
collect the results of the tests.  When the array is in self-test
mode, the main controller isolates the ram from the external inputs
by the use of multiplexor on the latched I/O boundaries.  The address
bus will be driven by the programmable up/down counter, the inputs to
the data bus are supplied by the data pattern generator, while the
output data bus is monitored by a comparator in the results
collection logic.

      Initially the macro begins in the "wait" state.  When the test
operation is to begin, an initialization sequence on the inputs
resets all internal latches to prepare for the test procedure.  From
this point forward no external inputs are required except for the
self-test clocks.

      After initialization, the controller will direct the dat...