Browse Prior Art Database

A CMOS Logic Circuit Using Common Gate Trench Devices

IP.com Disclosure Number: IPCOM000121833D
Original Publication Date: 1991-Sep-01
Included in the Prior Art Database: 2005-Apr-03
Document File: 1 page(s) / 34K

Publishing Venue

IBM

Related People

Chang, WH: AUTHOR

Abstract

Disclosed are two common gate trench FET devices built on two opposite sidewalls of a single trench. The two FET devices consist of a single NFET and a single PFET. The common gate material can be any material such as an n+ polysilicon or a W gate. Fig. 1 shows the cross section of the device and Fig. 2 shows the top view of the device. The devices can be used as a building block of a high density CMOS circuit family.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 100% of the total text.

A CMOS Logic Circuit Using Common Gate Trench Devices

      Disclosed are two common gate trench FET devices built on two
opposite sidewalls of a single trench.  The two FET devices consist
of a single NFET and a single PFET.  The common gate material can be
any material such as an n+ polysilicon or a W gate.  Fig. 1 shows the
cross section of the device and Fig. 2 shows the top view of the
device.  The devices can be used as a building block of a high
density CMOS circuit family.

      Disclosed anonymously.