Browse Prior Art Database

SOI CMOS and Bipolar Devices without Grain Boundary Defects

IP.com Disclosure Number: IPCOM000121838D
Original Publication Date: 1991-Sep-01
Included in the Prior Art Database: 2005-Apr-03
Document File: 1 page(s) / 55K

Publishing Venue

IBM

Related People

Ning, TH: AUTHOR [+4]

Abstract

Disclosed is a method for the placement of the active part of the MOS and Bipolar device, so that the defect formed when making SOI by epitaxial lateral overgrowth and chemical-mechanical polishing does not affect device operation.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 100% of the total text.

SOI CMOS and Bipolar Devices without Grain Boundary Defects

      Disclosed is a method for the placement of the active part of
the MOS and Bipolar device, so that the defect formed when making SOI
by epitaxial lateral overgrowth and chemical-mechanical polishing
does not affect device operation.

      When SOI is formed by epitaxial lateral overgrowth and
chemical-mechanical polishing, defect lines can be formed when the
films meet at 45 degrees or head on. If the active part of the
devices (i.e., MOS transistor channel or the bipolar transistor base)
are placed on these defect lines, the device may leak or just does
not function properly.

      In this disclosure it is proposed that the devices be placed in
the defect-free part of the film, so that the defect issue is
eliminated.  Since the location of the defect is known, the active
part of the device must be placed away from the defect by proper mask
design.  This is illustrated in Fig. 1 in which the active part of
the device is placed in the defect-free part of the film.

      Disclosed anonymously.