Browse Prior Art Database

A Self Aligned Poly-emitter Bipolar Transistor

IP.com Disclosure Number: IPCOM000121841D
Original Publication Date: 1991-Sep-01
Included in the Prior Art Database: 2005-Apr-03
Document File: 1 page(s) / 49K

Publishing Venue

IBM

Related People

Chang, W: AUTHOR [+5]

Abstract

Disclosed is a poly-emitter bipolar transistor having extrinsic-base link region formed by doped field oxide (BSG) to achieve self-aligned intrinsic collector region.

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A Self Aligned Poly-emitter Bipolar Transistor

      Disclosed is a poly-emitter bipolar transistor having
extrinsic-base link region formed by doped field oxide (BSG) to
achieve self-aligned intrinsic collector region.

      Compared with double-poly bipolar transistors, single-poly,
poly-emitter bipolar transistors are more suitable for BiCMOS process
because of their process compatibility with CMOS technology.  They
also reduce the process complexity while integrating high-voltage
analog and low-voltage high-speed logic devices on the same chip
because their EB linkup profiles vary easily with implant conditions.
Due to a simpler structure and lower topography, the scaling of the
single-poly,  poly-emitter transistor is more straightforward than
that of the double-poly transistor.  However, the performance and
density of the conventional poly-emitter bipolar transistors suffer
from a larger extrinsic CB junction area because of its
nonself-aligned collector region and direct contact on the base
diffusion region.  By using a doped field oxide layer to form an EB
linkup region (Fig. 1), the structure disclosed achieves a
self-aligned collector region while still maintaining flexibility in
EB linkup region design (Fig. 2).

      A possible process is illustrated as follows:
      1. Deposit and pattern BSG/nitride/oxide films.
      2. Form nitride sidewall (optional) and ion implant collector
(Fig. 1).
      3. Strip oxide/nitride, form BSG...