Browse Prior Art Database

Improved Control Voltage Level Translator for Variable Gain

IP.com Disclosure Number: IPCOM000121851D
Original Publication Date: 1991-Oct-01
Included in the Prior Art Database: 2005-Apr-03
Document File: 3 page(s) / 126K

Publishing Venue

IBM

Related People

Richetta, RA: AUTHOR [+2]

Abstract

Described is a novel voltage level translator which maximizes the control voltage range while tracking out the statistical variations of the NFET device in a Variable Gain Amplifier (VGA) which uses an NFET for modulating the gain.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 51% of the total text.

Improved Control Voltage Level Translator for Variable Gain

      Described is a novel voltage level translator which
maximizes the control voltage range while tracking out the
statistical variations of the NFET device in a Variable Gain
Amplifier (VGA) which uses an NFET for modulating the gain.

      The figure shows the schematic of the Variable Gain Amplifier
(VGA) with the improved control voltage level translator circuit.
The input to the VGA appears differentially at pins B0 and D0 and is
connected to the VGA through NFETs T3 and T4 when pin H0 is low.
When the H0 pin is high, NFETs T3 and T4 are off and the signal
is disconnected from the VGA.  Resistors R1 and R2 along with
external capacitors in series with the inputs serve to AC couple the
input signal to VREF (2.25 V), the voltage at pin V0.  The gain
modulating device is NFET T12, which is the emitter load of the first
differential gain stage formed by NPNs Q3 and Q4.  The collectors of
Q3 and Q4 drive load resistors R5 and R6.  The first stage is biased
by two 0.3 mA current sources J1 and J2.  The gain of the first stage
is modulated by the voltage at node 24.  As node 24 rises, the
channel resistance of T12 decreases, which increases the gain of the
first stage.  Likewise, as node 24 falls, the channel resistance of
T12 increases, which decreases the gain of the first stage.  The
output of the first stage drives the second stage through NPN emitter
followers Q5 and Q2, each of which is biased by 0.2 mA current
sources J7 and J8, respectively.  The second stage has a fixed gain
of about 5.5 and is formed by NPN differential pair Q16 and Q17 which
drive collector load resistors R7 and R4 and emitter resistor R3.
Bias for this stage is provided by J3 and J4 each of which conduct
0.3 mA.  Emitter followers Q15 and Q14 drive from the second stage to
the output stage and are biased at 0.2 mA by J9 and J10,
respectively.  The output stage is formed by Q7 and Q8 and drives two
external 100-ohm collector resistors which are terminated to the
+5-volt power supply.  The gain of the output stage is set by the
100-ohm external resistors along with resistor R8 to about 2.6.  The
output stage is biased by two 5.0 mA current sources J5 and J6.
Current source J13 along with PFET current mirror T1/T9 and diode
string Q11 and Q12 set the voltage at node 9 to VREF + 2*VBE.  This
provides the common mode level for the first two gain stages as well
as the base voltage for cascode NPNs Q6 and Q9.

      The remainder of the figure is the improved control voltage
level translator circuit that drives node 24.  A differential pair is
formed by NPNs Q1 and Q19 which is biased by two equal current
sources J15 and J16.  The collector currents of Q1 and Q19 are
mirrored by PFET current mirrors T7,T2 and T16,T14, respecti...