Browse Prior Art Database

Interface Protocol

IP.com Disclosure Number: IPCOM000121889D
Original Publication Date: 1991-Oct-01
Included in the Prior Art Database: 2005-Apr-03
Document File: 7 page(s) / 270K

Publishing Venue

IBM

Related People

Agha, SA: AUTHOR [+3]

Abstract

This article provides a simple protocol for time-insensitive, bidirectional, error-free communication between unchecked microprocessors. In addition, a "preemption without bias" feature differentiates real failures from response timeouts resulting from the unique real time processing and error recovery requirements of the independent processors at each end of the interface.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 23% of the total text.

Interface Protocol

      This article provides a simple protocol for
time-insensitive, bidirectional, error-free communication between
unchecked microprocessors.  In addition, a "preemption without bias"
feature differentiates real failures from response timeouts resulting
from the unique real time processing and error recovery requirements
of the independent processors at each end of the interface.

      In the disclosed implementation, this interface and protocol is
used to communicate between a processor in a device controller and an
operator panel processor in a system control panel (see Fig. 1).

      Data transfer from the initiator to the responder, i.e., write
commands, is in packets of 2 bytes.  The transaction is completely
interlocked and verified to provide error-free communication (see
Fig.  2).

      Controller Processor-Initiated Communication:  The controller
processor is the initiator and the panel processor is the responder
(see Fig. 3).

      The sequence of operation proceeds as follows:
1.   Before initiating communication, the initiator must verify it is
engaged in a previous transaction, either as initiator or responder.
      -    The HSB tag is checked for one (inactive tag) to verify
the panel processor has completed  a previously initiated transaction
(i.e., has recognized the clear from a previously initiated
transaction and is not hung in error state).
      -    The responders command register, Cc, is checked for zero
to avoid contention, to make sure the panel processor is not in error
recovery and can detect a new command via polling.
      -    HSA is activated to signal the start of communication.
This is an indication to the panel processor that the power control
processor is attempting to start communication.
2.   Once HSA is activated, the power control processor waits for 25
microseconds before loading its command register in order to defer to
the panel processor if it simultaneously initiated a command.
3.   When the 25-microsecond interval has elapsed, the panel
processors command register is checked again.
      -    If the initiator detects a non-zero value in Cc after the
25-microsecond interval, HSA is deactivated and this attempt is
aborted to defer to the command being initiated by the panel
processor.  The controller processor will wait until incoming the
command is complete before retrying.
      -    If the panel processors command register contains zero
after the 25-microsecond delay, the initiators data and command
registers are loaded to initiate the communication.  (The data
register must be loaded before the command register because panel
processor is monitoring the command register in order to detect the
next step in the handshake).
      -    In order for this contention mechanism to work, the panel
processor must load its command register within 20 microseconds of
detecting that HSA is inactive.
4.  ...