Browse Prior Art Database

Clock Acquisition and Recovery Technique for (1,k) Modulation Codes

IP.com Disclosure Number: IPCOM000121898D
Original Publication Date: 1991-Oct-01
Included in the Prior Art Database: 2005-Apr-03
Document File: 2 page(s) / 71K

Publishing Venue

IBM

Related People

Bailey, JA: AUTHOR [+3]

Abstract

In a tape drive magnetic recording system, a read data clock must be acquired from the recorded data. In the IBM 3480 tape drive system, this was accomplished by using a phase-locked loop (PLL). The 3480 recording channel uses a (0,3) modulation code. Therefore, the burst acquisition data pattern for 3480 is a 1111 ... pattern. The PLL must acquire lock to this pattern. The 3480 PLL is designed to have a free running frequency equal to the nominal data frequency. In addition, the PLL is designed to acquire lock within 30 data bits with an input data frequency range of +/- 15%.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Clock Acquisition and Recovery Technique for (1,k) Modulation Codes

      In a tape drive magnetic recording system, a read data
clock must be acquired from the recorded data. In the IBM 3480 tape
drive system, this was accomplished by using a phase-locked loop
(PLL). The 3480 recording channel uses a (0,3) modulation code.
Therefore, the burst acquisition data pattern for 3480 is a 1111 ...
pattern. The PLL must acquire lock to this pattern. The 3480 PLL is
designed to have a free running frequency equal to the nominal data
frequency. In addition, the PLL is designed to acquire lock within 30
data bits with an input data frequency range of  15%.

      Future tape drive products will probably use the (1,7)
modulation code. This code has many advantages over the (0,3) code.
However, this code must have at least one "zero" between consecutive
"ones" which requires having a voltage controlled oscillator (VCO)
which operates at twice the data pulse frequency. Therefore, the PLL
must acquire lock with a 1010 ... burst pattern. This means that the
PLL only receives 1/2 of the read data information as it did with the
(0,3) modulation code. It has been demonstrated in the lab and also
with computer-aided simulation that the PLL can have several stable
operating points when using a (1,7) code. The PLL acquires a stable
lock either in phase with the data pulses or  90 degrees
out-of-phase if the (1,7) code is used. This problem will occur when
there is a difference greater...