Browse Prior Art Database

Embedded Sequential Coding During Steady State Control Conditions

IP.com Disclosure Number: IPCOM000121902D
Original Publication Date: 1991-Oct-01
Included in the Prior Art Database: 2005-Apr-04
Document File: 6 page(s) / 250K

Publishing Venue

IBM

Related People

Abdelnour, G: AUTHOR [+4]

Abstract

The ability to maintain control states when performing subordinate functions over a set of signal lines (single line being a special case) is required to control a common interface but allow specific functions to occur. The specific problem is to hold a logical attachment to a common bus in the inactive, disabled, or reset state, during specific condition inquiries. This must be performed in a manner that prevents accidental activation while issuing status responses, internal enables, or sequenced set-up commands. Also, this must not require additional interconnect signals, or cause the loss of the previously established primary state.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 26% of the total text.

Embedded Sequential Coding During Steady State Control Conditions

      The ability to maintain control states when performing
subordinate functions over a set of signal lines (single line being a
special case) is required to control a common interface but allow
specific functions to occur.  The specific problem is to hold a
logical attachment to a common bus in the inactive, disabled, or
reset state, during specific condition inquiries.  This must be
performed in a manner that prevents accidental activation while
issuing status responses, internal enables, or sequenced set-up
commands.  Also, this must not require additional interconnect
signals, or cause the loss of the previously established primary
state.

      This invention describes a method of coding commands or
functions into a control interconnect having a limited number of
signals while preserving the previously defined static conditions.
This may be accomplished simultaneously (dual function capability)
from a predefined state or condition, or by allowing embedded
sequences of related or progressive control stages to be performed
concurrently.

      The method is based on the recognition of encoded or simplex
bus signals that define requests or instructions for steady-state
conditions and is expandable to include complex relationships via the
quantity and ordering of their encoded occurrence.  By defining the
valid sequences, the steady-state conditions can be maintained while
performing other required tasks.
 .   REDUCE BUS LINES/COMPONENTS:  By embedding additional codes on
existing signal/bus lines, the actual number of lines and
driver/receivers can be held to a minimum. This is even more
important in a design which requires fault tolerance, since fault
tolerance is normally accomplished by duplexing signals.
 .   FAULT TOLERANCE:  The time sequence encoding of commands on
existing signal lines yields an additional level of fault tolerance
and protection against erroneous function activation.  This is true
because a sequence of operations are required to activate any given
function.
 .   STATE CONTROL:  By holding the required steady-state override
conditions at the poll master, the proper commands can be issued
without knowing the state and/or presence of an adapter/slot.  If
special commands are used, the steady-state conditions can be
maintained without having to issue additional commands.  This is very
important in an unattended system where adapters may be added,
removed, or disabled without the need for any monitoring to insure
bus integrity.

      The additional complexity at each adapter/slot and the poll bus
master to sequence and/or detect the embedded coding is a detriment.
But, with the density of VLSI, PAL, and GAs, this becomes quite
trivial.

      In a parallel multi-drop bus environment, commands are
distributed via a control bus using encoded addresses for selection,
and encoded commands to activate mutually exclusiv...