Browse Prior Art Database

Memory Self Test

IP.com Disclosure Number: IPCOM000121915D
Original Publication Date: 1991-Oct-01
Included in the Prior Art Database: 2005-Apr-04
Document File: 2 page(s) / 42K

Publishing Venue

IBM

Related People

Chen, CL: AUTHOR [+5]

Abstract

Disclosed is an apparatus for the self-test of a computer memory. The fault detection coverage is achieved with a minimum of software and hardware support.

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This is the abbreviated version, containing approximately 100% of the total text.

Memory Self Test

      Disclosed is an apparatus for the self-test of a computer
memory.  The fault detection coverage is achieved with a minimum of
software and hardware support.

      The data pattern register is used to hold a predefined seed for
the linear feedback shift register (SR) in generating pseudo random
test patterns.  Two modes of operations are built in the SR
controlled by the two switches: one for the 16-pattern test and one
for the 146- pattern test.  The following is the test procedure for
each operation mode:
      1.   Initialize the SR with a seed.
      2.   Generate test pattern by shifting the register and store
pattern throughout the storage space.  Fetch the data starting from
address 0 and compare with pattern regenerated from the same seed.
      3.   Repeat Step 2 with complement of the SR data.
      4.   Using the last data from SR as a new seed, repeat Steps
2-3 seven more times for the 16-pattern test and 72 more times for
the 146-pattern test.

      In either test, any pair of cells would see all 4 2-bit
patterns, 00, 01, 10 and 11.  The 16-pattern test covers all single
or double bit stuck-at faults and two-bit data bridge fault in a
72-bit word.  The 146-pattern test detects double bit faults in the
entire memory, including multiple address stuck faults and decoder
faults in any array or sub-array of the memory chip, and bridge
faults.