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Weighted Control Voltage Generator for the Voltage Controlled Oscillator of a Phase Locked Loop

IP.com Disclosure Number: IPCOM000121928D
Original Publication Date: 1991-Oct-01
Included in the Prior Art Database: 2005-Apr-04
Document File: 3 page(s) / 98K

Publishing Venue

IBM

Related People

Chen, YC: AUTHOR [+6]

Abstract

This article addresses a new, improved and simpler version of a VCO (voltage controlled oscillator) generator circuit that is used in a Phase-Locked Loop (PLL). The new circuit consumes less power and occupies less chip area than the old, as well as making unnecessary loading block and other circuits.

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Weighted Control Voltage Generator for the Voltage Controlled Oscillator
of a Phase Locked

Loop

      This article addresses a new, improved and simpler
version of a VCO (voltage controlled oscillator) generator circuit
that is used in a Phase-Locked Loop (PLL).  The new circuit consumes
less power and occupies less chip area than the old, as well as
making unnecessary loading block and other circuits.

      Dual-phase lock loop (DPLL) clock recovery design for single
chip implementation places a premium on circuit simplification,
power, and chip area requirements.  Clock recovery is used to
generate required timing information from a serial input data stream
whose transmitter is remotely located.  The clock recovery circuit is
implemented using a DPLL approach in which two standard PLLs are
loosely coupled to achieve the required performance, as illustrated
in the general block diagram in Fig. 1.  A low frequency reference
(e.g., system clock) 1 is input to the first PLL which acts as a
frequency synthesizer.  The loop adjusts the frequency of VCO1 2 to
be N times that of the reference input 1.  The same control voltage
seen by 2 is used to bias the second oscillator VCO2 3.  Because the
two oscillators are constructed on the same chip the two frequencies
will track closely and so the free-running frequency of 3 is
precisely controlled relative to a stable source.  The second PLL
fine tunes the second oscillator to achieve phase synchronism with
the input data.

      Existing VCO generator circuit design for the PLL employs three
pairs of unit gain amplifiers (or voltage followers) to generate
three control voltages, i.e., VPR1A, VPR1B and VPR2, which control
the oscillating frequencies of the VCOs 2 and 3.  VPR1A and VPR1B are
two identical voltages.  VPR1A controls all 11 stages of 2, the
reference loop, while VPR1B controls two stages in the loading block
and 9 stages in 3, the data loop.  VPR2 controls 9 stages in t...