Browse Prior Art Database

Power On Reset Control Mechanism for Multiprocessor System

IP.com Disclosure Number: IPCOM000121951D
Original Publication Date: 1991-Oct-01
Included in the Prior Art Database: 2005-Apr-04
Document File: 2 page(s) / 65K

Publishing Venue

IBM

Related People

Murata, H: AUTHOR [+3]

Abstract

Disclosed is a new power-on reset mechanism for shared bus multiprocessor systems. This mechanism provides a fault-tolerant and flexible environment for power-on reset with a self-test.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 54% of the total text.

Power On Reset Control Mechanism for Multiprocessor System

      Disclosed is a new power-on reset mechanism for shared
bus multiprocessor systems.  This mechanism provides a fault-tolerant
and flexible environment for power-on reset with a self-test.

      The disclosed mechanism has the following features:
1.  The system can be booted if at least one CPU module survives.
2.  If a fatal error is detected in a CPU module during the system
test, the system can continue the test by detaching the module.
3.  This mechanism does not depend on the number of CPU modules.
4.  This mechanism is implemented with a simple hardware, which
utilizes the arbitration lines, and therefore does not require any
additional bus signals.

      The figure depicts the hardware block diagram of the reset
mechanism.  ASN (All Slot Number) is an input port that indicates the
total number of slots in the system. SNO (Slot Number) is also an
input port that identifies the slot number.  POR (Power On Reset) is
an input port that initializes the CPU and the bus controller.  POR
is activated at the system initialization phase.  Note that CPU-1
need not to be installed in slot-1, and furthermore some slots can be
vacant.

      The procedure of system reset is as follows:
1.  POR is activated.  All bus controllers detach CPU modules from
the system bus.  All hardware components are initialized.
2.  POR is deactivated.  Each bus controller counts the bus cycle
after POR goin...