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Buffering Method for Serial Frames

IP.com Disclosure Number: IPCOM000121968D
Original Publication Date: 1991-Oct-01
Included in the Prior Art Database: 2005-Apr-04
Document File: 4 page(s) / 140K

Publishing Venue

IBM

Related People

Miracle, G: AUTHOR [+2]

Abstract

A method is presented for buffering of multiple serial frames, maintaining chronological order of frame reception, with minimal hardware overhead. A dual-port buffer is used, in which frames and their associated byte counts are stored. Through the use of a "count address" register, the byte count is stored in the buffer location immediately preceding the frame with which it is associated.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 49% of the total text.

Buffering Method for Serial Frames

      A method is presented for buffering of multiple serial
frames, maintaining chronological order of frame reception, with
minimal hardware overhead.  A dual-port buffer is used, in which
frames and their associated byte counts are stored. Through the use
of a "count address" register, the byte count is stored in the buffer
location immediately preceding the frame with which it is associated.

      A serial system component is required to store a finite number
(n) of variable length frames received from a high-speed link.  The
;number of size range of the frames to be buffered is determined by
architecture protocols in effect.  These frames must be stored in
chronological order for further processing by separate logic (in some
cases a microprocessor).  The goal is to buffer the frames and any
additional status required with a minimal amount of hardware.

      The first approach considered was the use of n buffers, each
capable of storing one maximum length frame.  The buffers are filled
sequentially with one frame each. Additional hardware is required to
store the byte count contained in each buffer and to control the
multiplexing and de-multiplexing involved in writes and reads.  This
approach was abandoned due to the potentially wasted buffer space and
complex control logic.

      The next approach considered was the storage of all the frames
in one dual-port buffer allowing frame writing to occur while
previous frames are being read and further processed by other logic.
In order to properly read the frames from the buffer, control logic
is required to save the start and end locations of each frame.
Proper coordination of the control logic with specific frames for
transfers of information to the frame processing logic was
cumbersome, but less buffer space was required.

      Storing the byte count of each frame in the buffer, immediately
preceding the beginning of the frame, reduced the complexity of the
control logic.  The problem to be solved with this approach was how
to store this frame status and count field, which is only known at
the end of each frame reception, in the locations preceding the first
byte of the frame.  The mechanism for doing this was the use of a
"count address" register.  This concept is described below.

      During hardware initialization, before reception for the first
frame, the count address register and write byte counter and a read
pointer are all set to zero.  A write pointer is initialized to point
to location "w," where w equals the number of bytes required to store
the frame status and byte count field (see Fig. 1).  When the first
frame is received, it is buffered using the write pointer in
ascending locations starting at address w, with the write pointer and
write byte counter being incremented after each byte is written into
the buffer.  After this first frame is completely buffered, then the
length of this frame is contain...