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Enhanced Memory Addressing Diagnostics for Intermediate Systems

IP.com Disclosure Number: IPCOM000121979D
Original Publication Date: 1991-Oct-01
Included in the Prior Art Database: 2005-Apr-04
Document File: 3 page(s) / 91K

Publishing Venue

IBM

Related People

Haselhorst, KH: AUTHOR

Abstract

Main store address testing can be completely checked in a relatively short time. This is accomplished by splitting the function to match the hardware implementation. In most cases, it is split into card addressing, module addressing, and cell addressing.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Enhanced Memory Addressing Diagnostics for Intermediate Systems

      Main store address testing can be completely checked in a
relatively short time.  This is accomplished by splitting the
function to match the hardware implementation.  In most cases, it is
split into card addressing, module addressing, and cell addressing.

      Instead of crunching a huge number of patterns into main store,
it can be checked more thoroughly by breaking down the function of
the patterns.  By splitting the address test into several parts, it
is possible to speed it up while increasing its ability to pinpoint
where the error exists.

      The first part is to check the card addressing.  By using a
single address within each card, the test can determine whether the
correct card is being selected.  This function is partially on the
CPU (select logic) and partially on the main store cards (receivers
and/or destination logic).  (See Fig. 1.)

      The next step is to test module addressing.  This test will
require knowledge of the logical layout of the main store cards;
however, a single design may check several layouts.

      This test is also very simple.  It requires memory to be
initialized to a background pattern ('0'b) because memory is designed
with only a single bit from each module in an ECC word.  A 'group' of
modules (one for each bit) is addressed at any one time.  By writing
a unique pattern into each group, the higher order address lines and
the module select logic is tested.  Main store will need to be
fetched and checked in its entirety to check for shorted address
lines. (See Fig. 2.)

      The final part of the test is the cell addressing test. This
test will, in essence, write a diagonal of bits through each array
module.  This will test each RAS and CAS decode within the chips, and
also ch...