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Browse Prior Art Database

Generic Processor Modeller

IP.com Disclosure Number: IPCOM000121985D
Original Publication Date: 1991-Oct-01
Included in the Prior Art Database: 2005-Apr-04
Document File: 4 page(s) / 146K

Publishing Venue

IBM

Related People

Gariazzo, RE: AUTHOR

Abstract

When designing a CPU complex, one of the most important aspects is the performance the design will have when stamped on silicon. There are several tools available to evaluate the performance of a system --computer aided tools, software models (TIMERS)-- but all these tools become usable too late in the system development cycle.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 42% of the total text.

Generic Processor Modeller

      When designing a CPU complex, one of the most important
aspects is the performance the design will have when stamped on
silicon.  There are several tools available to evaluate the
performance of a system --computer aided tools, software models
(TIMERS)-- but all these tools become usable too late in the system
development cycle.

      One solution to the early need for a system performance
evaluation would be a software model accurate enough to be within 10%
of the real system, but also flexible enough to rapidly test new
changes and new configurations early in the design cycle.  This tool,
called the "Generic Processor Modeller", is the subject of this
article.

      Cycle Timer Register Level Simulators, or TIMER, have a long
design and implementation cycle, because they are a very close
representation of the hardware implementation. But, as advantageous
as this low level representation can be to do system analysis, it
brings a rigidity that makes the TIMER a poor tool to evaluate design
changes and variations in the implementation, early in the design
cycle.

      There is a need for a tool to provide the designers with the
means to represent any architecture implementation, without a large
investment of time and effort.  The designers, by means of a
high-level representation, should be able to specify the desired
implementation and test it for performance.

      The Generic Processor Modeller is a comprehensive tool that
intends to address these flexibility needs and high-level language
representation issues.

      The Generic Processor Modeller is a software model, or TIMER--
not fixed to an established system implementation. It has parameters
allowing the user to specify the desired system configuration to test
for performance.  The output is also configurable and it gives
detailed information of each instruction, as it goes through the
internal pipeline defined by the user.

      Since the configuration of the system is completely user-
dependent, this model does not have a fixed concept of stages or
units inside it, as a Decode unit or an Execution unit.  Its general
implementation is held by the definition of resources that are used
in the system, how they act internally and how they behave with the
other units.  There are three kind of resources the Generic Processor
Modeller uses:  Execution Unit, Memory Unit and Bus.  In this manner,
if the system to be configured has a decode stage and an execute
stage with a cache module, the Generic Processor Modeller would have
three units defined: one execution unit for each of the two stages
(decode and execute), and one memory unit for the cache.  Also it
would have the buses (data, address and instruction) which would
connect the three stages.

      The basic building blocks of the Generic Processor Modeller
are:  'Execution Unit', 'Memory Unit' and Buses. The 'Execution Unit'
is defined as a stage in a syst...