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Trench Capacitor and Dry Etching Technique of Forming Same with Increased Capacitance Density Relative to Conventional Trench Capacitor

IP.com Disclosure Number: IPCOM000121996D
Original Publication Date: 1991-Oct-01
Included in the Prior Art Database: 2005-Apr-04
Document File: 3 page(s) / 96K

Publishing Venue

IBM

Related People

Kleinhenz, RL: AUTHOR [+2]

Abstract

Disclosed is a method for a simplified fabrication process for a "balloon"-type trench capacitor which is described in [1]. A capacitor with increased capacitance density is formed by a combination of directional Cl-based etching and isotropic F-based etching, exploiting sidewall passivation to increase the area of the trench in a controlled fashion. There is no need for an additional masking step.

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Trench Capacitor and Dry Etching Technique of Forming Same with Increased
Capacitance Density Relative to Conventional Trench Capacitor

      Disclosed is a method for a simplified fabrication
process for a "balloon"-type trench capacitor which is described in
[1].  A capacitor with increased capacitance density is formed by a
combination of directional Cl-based etching and isotropic F-based
etching, exploiting sidewall passivation to increase the area of the
trench in a controlled fashion. There is no need for an additional
masking step.

      Increased density of dynamic random-access memories on a chip
requires downscaling of the lateral dimensions of the storage
capacitor while keeping the capacitance roughly the same. Assuming
that the dielectric remains SiO2 and the thickness of the dielectric
cannot be further reduced because of reliability considerations, the
straightforward approach to compensating for the reduced lateral area
of the capacitor is to increase the trench depth.  For a 64 MBit chip
the depth of the capacitor is on the order of 10 mm and with the
lateral dimensions of 0.4 mm. These trench dimensions are close to
what can be fabricated because of aspect-dependent slow-down of the
reactive ion etch rates and throughput considerations (about 30
minutes per wafer are required to shape the storage capacitor for the
64 MBit trench geometry).

      The process described in (1) uses a combination of (1)
directional trench etching, (2) reoxidation of the trench, (3)
reactive ion etching of the oxide on the bottom of the trench, and
(4) subsequent isotropic etching.  In the process disclosed here
steps (3) and (4) of (1) can be avoided.

      The directional Si trench etch is performed using...