Browse Prior Art Database

Unexpected Reset Recovery Strategy for a Distributed Power Network

IP.com Disclosure Number: IPCOM000121997D
Original Publication Date: 1991-Oct-01
Included in the Prior Art Database: 2005-Apr-04
Document File: 3 page(s) / 92K

Publishing Venue

IBM

Related People

Berglund, NC: AUTHOR [+2]

Abstract

Described is a simple method for recovering safely from an unexpected software or hardware reset in a microprocessor-controlled system. This is especially important in applications in which external device power is under the direct control of the microprocessor. An unexpected reset of the processor may cause the power control variables to be reinitialized and thus the power state of the devices may be lost.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Unexpected Reset Recovery Strategy for a Distributed Power Network

      Described is a simple method for recovering safely from
an unexpected software or hardware reset in a
microprocessor-controlled system.  This is especially important in
applications in which external device power is under the direct
control of the microprocessor.  An unexpected reset of the processor
may cause the power control variables to be reinitialized and thus
the power state of the devices may be lost.

      In any microprocessor-controlled system, the possibility of an
unexpected reset is inevitable.  Watchdog timeouts, wild branches
into unused code space, stack corruption, or glitches on the reset
line itself are all possible problems which may lead to a reset.  If
there are devices in the system which rely on the microprocessor for
power control, the result of this reset can be devastating. As the
power control variables are reinitialized, the individual devices may
suddenly power off or on.  Depending on the specific application one
or both of these possible outcomes may be unacceptable.  Thus, a
method for recovering from the error without changing the power state
of the device is needed.

      Refer to the figure for the following description of the
restart algorithm.

      The microprocessor used in this example contains a
bit-addressable Power Control register (PCON).  A flag in PCON called
POF (Power-Off Flag) is used to signal warm or cold starts.  When VCC
rises from 0 to 5 V  (cold start), POF will be set by the processor
hardware.  The flag can now be set or cleared by software.

      At the top of the software Power-On Reset (POR) routine, POF is
checked.  POF = 1 indicates that a cold start is required.  Then POF
is cleared to signal that a cold start has occurred, and normal
initialization and Basic Assurance Tests (BATs) are performed.

      If POF was already clear at the start of POR initialization,
the software knows that a cold start has already occurred and an
attem...