Browse Prior Art Database

Uniform Selective Epitaxy in a Vertical Reactor

IP.com Disclosure Number: IPCOM000122027D
Original Publication Date: 1991-Oct-01
Included in the Prior Art Database: 2005-Apr-04
Document File: 2 page(s) / 86K

Publishing Venue

IBM

Related People

Kuge, HH: AUTHOR

Abstract

4-megabit memory chips are produced in a process cycle during which an epitaxial silicon layer is applied to the wafers by chemical vapor deposition (CVD). The Si layer grows only in bare poly- or monocrystalline silicon areas. There is no deposition on silicon oxide, which is prevented by admixing a particular dose of special reaction gases to the reaction mixture (selective epitaxy).

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Uniform Selective Epitaxy in a Vertical Reactor

      4-megabit memory chips are produced in a process cycle
during which an epitaxial silicon layer is applied to the wafers by
chemical vapor deposition (CVD).  The Si layer grows only in bare
poly- or monocrystalline silicon areas. There is no deposition on
silicon oxide, which is prevented by admixing a particular dose of
special reaction gases to the reaction mixture (selective epitaxy).

      An epitaxial reactor widely used for this purpose is of the
vertical type.  The flow system consists of a flat graphite disk with
pockets for the wafers which are covered by a quartz dome.  The
planar susceptor has an opening in its center through which the gases
are led into the reactor. A high-frequency coil heating the susceptor
and the wafers in the pockets by inductive coupling is positioned
below the susceptor.  Because of its high gradient (about 5 nm/~C),
the temperature is a critical deposition parameter.

      As the heated wafers tend to bend and the distance between the
bottom edge of the wafer and the top surface of the susceptor
determines the heat flow to the wafer, the wafer pockets have a
matching, calotte-shaped profile. Uniform temperature distribution is
obtained where the profiles of the pockets and the wafer warpage
match.  The thickness of the deposited silicon layer should roughly
follow the temperature profile.  For a uniform deposition process,
the ideal pocket shape has to be determined for a particular type of
wafer and process temperature.

      Several measurements on different wafers have shown that the
results obtained with regard to uniformity are not optimal.
Normally, the thickness profile of the deposited silicon is also
calotte-shaped. When wafers of a particular type all bend to the same
extent (radius of curvature r), the radius of the calotte-shaped
pocket should be identical in an ideal case, so that at a particular
radius r or pocket depth for a fixed pocket diameter, the distance
between the top edge of the susceptor and the bottom edge of the
wafer would be zero at any point on the wafer.  If the pocket is too
...