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Parallel Binary and Hex Normalizer for Floating Point

IP.com Disclosure Number: IPCOM000122048D
Original Publication Date: 1991-Oct-01
Included in the Prior Art Database: 2005-Apr-04
Document File: 1 page(s) / 46K

Publishing Venue

IBM

Related People

Karim, FO: AUTHOR [+2]

Abstract

The problem in this Processor design is to Normalize the results of the Floating Point operations as fast as possible, without using a large number of circuits. One speed-up technique is to generate the binary and Hex select lines in parallel. This design requires a lot of circuits. Serialized select logic gives the minimum hardware cost by sacrificing performance. The goal was to design the select logic with a minimum hardware cost without sacrificing performance.

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Parallel Binary and Hex Normalizer for Floating Point

      The problem in this Processor design is to Normalize the
results of the Floating Point operations as fast as possible, without
using a large number of circuits.  One speed-up technique is to
generate the binary and Hex select lines in parallel.  This design
requires a lot of circuits. Serialized select logic gives the minimum
hardware cost by sacrificing performance.  The goal was to design the
select logic with a minimum hardware cost without sacrificing
performance.

      The Hex Normalizer is so long (approximately 100 bits) that
buffering the Hex selects would be required.  However, a buffer this
large is fairly slow and has a large capacitance on its inputs.

      If the unbuffered Hex selects were tapped to select the first
four bits of the Hex normalizer, the data to calculate the binary
selects would arrive ahead of the data to be normalized.  This is the
exact same binary select logic used for serial select design (i.e.,
the smallest circuit possible).  However, this fast buffering
technique gives the appearance of the Binary select logic being done
in parallel with the Hex Normalization.  Since the "Buffer" has such
a high input capacitance, tapping off for 4 bits does not appreciably
slow down the Hex data path.

      The binary and hex selects are generated with minimum circuits,
with the binary selects having the appearance of being done in
parallel with the hex selects.

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