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Artifact Topography to Facilitate Planarization Measurements

IP.com Disclosure Number: IPCOM000122080D
Original Publication Date: 1991-Oct-01
Included in the Prior Art Database: 2005-Apr-04
Document File: 1 page(s) / 34K

Publishing Venue

IBM

Related People

Gut, GM: AUTHOR [+2]

Abstract

Certain semiconductor processes require planarization of oxide layers which are applied on top of varying height features on wafers. Measurement of the quality of this planarization is difficult due to the presence of a variety of substrates on the wafer. To solve this problem a single, well-understood substrate is substituted for the various layers on the wafer. An artifact topography, which accurately replicates the wafer topography, is constructed in the substitute wafer.

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Artifact Topography to Facilitate Planarization Measurements

      Certain semiconductor processes require planarization of oxide
layers which are applied on top of varying height features on wafers.
Measurement of the quality of this planarization is difficult due to
the presence of a variety of substrates on the wafer.  To solve this
problem a single, well-understood substrate is substituted for the
various layers on the wafer.  An artifact topography, which
accurately replicates the wafer topography, is constructed in the
substitute wafer.

      A silicon wafer is patterned with photoresist using mask layers
which generate topography.  The wafer is then subjected to an etch
process which removes an amount of silicon which duplicates the
topography contribution from that level.  All the contributing layers
are patterned in sequence.  The final topography accurately mimics
actual topography but is devoid of the various materials present on
an actual wafer.  Measurements of thickness on silicon are very easy
to perform and are very accurate.  This permits quick, easy and
accurate evaluation of processes which perform planarization of oxide
on top of topography.

      Disclosed anonymously.