Browse Prior Art Database

A Multi-ported Memory Array Optimized for Sequential Transfers

IP.com Disclosure Number: IPCOM000122088D
Original Publication Date: 1991-Oct-01
Included in the Prior Art Database: 2005-Apr-04
Document File: 1 page(s) / 50K

Publishing Venue

IBM

Related People

Freitas, RF: AUTHOR [+2]

Abstract

This disclosure describes a memory array design that is optimized for large sequential transfers. It provides high performance while providing access to multiple requests.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 74% of the total text.

A Multi-ported Memory Array Optimized for Sequential Transfers

      This disclosure describes a memory array design that is
optimized for large sequential transfers.  It provides high
performance while providing access to multiple requests.

      A multi-way interleaved memory is used for high throughput.
When one memory bank is busy servicing a particular port, other ports
can access any one of the remaining memory banks.  In the current
embodiment, an 8-way interleave scheme is used.

      To reduce access latency, all memory banks are operated
asynchronously. A memory access request is serviced by the target
memory bank as soon as it comes in regardless of the states of the
other memory banks.

      The address assignment for each bank is arranged such that a
requesting port will access a relatively small number of bytes before
moving on to the next bank.  This provides a bound to the length of
time that a requesting port can keep a memory bank busy before
relinquishing it.  In the current embodiment, the address is arranged
such that a requesting port can only access 32 bytes at a time.  So
if a requesting port is waiting on a memory bank which is currently
busy servicing another port, the requesting port does not have to
wait more than the time it takes to access 32 bytes.

      To reduce the amount of time to access the memory in each bank,
a wide memory arrangement is used that allows multiple bytes to be
accessed in each memory cycle. ...