Browse Prior Art Database

External Control of an Internal State Machine

IP.com Disclosure Number: IPCOM000122130D
Original Publication Date: 1991-Nov-01
Included in the Prior Art Database: 2005-Apr-04
Document File: 2 page(s) / 77K

Publishing Venue

IBM

Related People

Bischoff, G: AUTHOR [+3]

Abstract

A critical area in gate array or VLSI device design is the external interface. Internal logic can be simulated resulting in a reliable design that is correct the first time. It is much more difficult to do the external interface design. Many times the external interface portion of a gate array or VLSI chip uses state machines to control a sequence of events and/or timing. A method of controlling the action inside the gate array or VLSI device would be beneficial. If the external circuitry changes or is not clearly defined, the device must often be redesigned, which impacts the schedule and cost of a project. Rather than redesign the gate array or VLSI device, we have come up with a novel way of controlling the action of a state machine by way of external inputs.

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This is the abbreviated version, containing approximately 52% of the total text.

External Control of an Internal State Machine

      A critical area in gate array or VLSI device design is
the external interface.  Internal logic can be simulated resulting in
a reliable design that is correct the first time.  It is much more
difficult to do the external interface design.  Many times the
external interface portion of a gate array or VLSI chip uses state
machines to control a sequence of events and/or timing.  A method of
controlling the action inside the gate array or VLSI device would be
beneficial.  If the external circuitry changes or is not clearly
defined, the device must often be redesigned, which impacts the
schedule and cost of a project.  Rather than redesign the gate array
or VLSI device, we have come up with a novel way of controlling the
action of a state machine by way of external inputs.  The buried
logic that usually must change is that of the state  machine.   This
solves the problem of committing a critical state machine logical
function or timing function into a gate array or VLSI chip. This
interface provides a method of controlling state machine(s) inside a
gate array, if control is necessary.  If control is not necessary, no
external circuitry is required.

      This invention is used to alter the timing of a state machine
inside a gate array or VLSI chip.  As shown in the figure external
circuitry is added which monitors the state outputs of the state
machine in the gate array.  The external circuitry is not
incorporated unless there is a need  to  modify the state timing.
This is particularly useful when interfacing to external circuitry
that could change.  For example, this concept is used to interface an
array to an external memory. Memory timing parameters could change as
new memory technology becomes available or devices from di...