Browse Prior Art Database

MRU Update Control for Multiple Level Caches

IP.com Disclosure Number: IPCOM000122134D
Original Publication Date: 1991-Nov-01
Included in the Prior Art Database: 2005-Apr-04
Document File: 2 page(s) / 71K

Publishing Venue

IBM

Related People

Huang, KS: AUTHOR [+3]

Abstract

Disclosed is a technique for updating cache line activeness between different cache hierarchies. The central idea is to periodically update certain MRU information of first level cache to second level. The control of update may utilize free first level cache directory cycles.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

MRU Update Control for Multiple Level Caches

      Disclosed is a technique for updating cache line
activeness between different cache hierarchies.  The central idea is
to periodically update certain MRU information of first level cache
to second level.  The control of update may utilize free first level
cache directory cycles.

      In a computer system with multiple levels of cache hierarchies
there are often undesirable line replacements at a lower level due to
the lack of knowledge on certain access activities from the
processors.  Consider a uniprocessor system with 2 levels of caches:
L1 and L2.  L1 is directly accessed by the processor.  Upon L1 cache
miss the line is fetched from L2 (further fetch from L3 is involved
if L2 misses as well).  Upon such L1 miss fetch, the associated L2
line is made MRU (Most-Recently-Used) in its congruence class as
normal practice.  In such a typical design approach, an L1 line may
be frequently accessed by the processor, while the associated L2 line
gets aged out quickly.  For various reasons it is desirable to keep
those L2 lines in L2 that are relatively frequently accessed by the
processor.  This is particularly true when L1 is maintained as a
subset of L2, since L2 replacement will force the invalidation of
corresponding L1 line(s).

      In order to remedy the above mentioned deficiency on L2
replacements of lines frequently accessed (by processor), the L2
replacement status should be updated in order to avoid the aging of
such lines by conventional LRU replacement algorithms.

      The invention will be illustrated using the above described
L1/L2 example.  The basic idea is to create a control that scans
through the congruence classes of L1 and periodically issues L2 line
MRU update requests.  In th...