Browse Prior Art Database

Error Detection and Reporting in Fault Tolerant Computer

IP.com Disclosure Number: IPCOM000122138D
Original Publication Date: 1991-Nov-01
Included in the Prior Art Database: 2005-Apr-04
Document File: 5 page(s) / 114K

Publishing Venue

IBM

Related People

Cheng, C: AUTHOR [+2]

Abstract

Disclosed is a method for checking out the error detection/correction/reporting circuitries in the machine that has advanced error correction features, such as bit steering and memory remap capabilities.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Error Detection and Reporting in Fault Tolerant Computer

      Disclosed is a method for checking out the error
detection/correction/reporting circuitries in the machine that has
advanced error correction features, such as bit steering and memory
remap capabilities.

      Referring to Fig. 1, a computer system is generally designated
by the reference number 10.  Computer system 10 includes a central
processor 12 and main memory 14.  A cache subsystem 16 is located
between the central processor 12 and the main memory 14.  Data and
address lines connect the central processor 12 to the cache 16 and
connect the cache 16 to the main memory 14.  In special
circumstances, data lines 18 and address lines 20 can be used to
bypass the cache 16 and give the central processor 12 direct access
to main memory 14.  The re mainder of the system 10, including mass
storage and input/output devices, is conventional and is not shown in
Fig. 1.

      Fig. 2 illustrates the high-level organization of main memory
14.  Main memory 14 includes a data memory portion 22 and an Error
Correcting Code (ECC) data portion 24.  The contents of the data
memory are normally accessible by user applications, while the
contents of the ECC data memory 24 are generally only accessible to
error checking hardware portions of the system and are not accessible
to user applications.  In special circumstances, in order to perform
testing, direct access can be made to the ECC data memory 24 by an
executing application.  This is referred to as PIO load and store in
this article.

      RISC System/6000* implements bit steering as a mem...