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High Density CMOS SRAM Cell

IP.com Disclosure Number: IPCOM000122146D
Original Publication Date: 1991-Nov-01
Included in the Prior Art Database: 2005-Apr-04
Document File: 3 page(s) / 76K

Publishing Venue

IBM

Related People

Chang, WH: AUTHOR

Abstract

This article describes a high-density CMOS SRAM cell. The basic cell is achieved by a close-coupled CMOS inverter circuit. Both PFET load device and NFET driver device are located inside the same trench and occupy opposite sides of the trench. The access transfer device is a NFET planar device. The vertical and top cross sections of half of the SRAM cell are shown in Figs. 1 and 2. A possible layout of the SRAM cell is shown in Fig. 3 with its equivalent circuit shown in Fig. 4. The power is applied on the cell through a buried p+ diffusion which is the source of the PFET load device. The sources of the driver NFET devices are tied to ground through buried n+ source diffusions. The word line, W/L, controls the signal transfer to and from the bit lines, B1,B2, through NFET transfer devices.

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High Density CMOS SRAM Cell

      This article describes a high-density CMOS SRAM cell.
The basic cell is achieved by a close-coupled CMOS inverter circuit.
Both PFET load device and NFET driver device are located inside the
same trench and occupy opposite sides of the trench.  The access
transfer device is a NFET planar device.  The vertical and top cross
sections of half of the SRAM cell are shown in Figs. 1 and 2.  A
possible layout of the SRAM cell is shown in Fig. 3 with its
equivalent circuit shown in Fig.  4.  The power is applied on the
cell through a buried p+ diffusion which is the source of the PFET
load device.  The sources of the driver NFET devices are tied to
ground through buried n+ source diffusions.  The word line, W/L,
controls the signal transfer to and from the bit lines, B1,B2,
through NFET transfer devices.  The transfer devices are planar FET
devices.  This SRAM cell occupies a much smaller area than that of
the cell that uses planar FET devices.