Browse Prior Art Database

Direct Memory Access-Based Integrated Services Digital Network Telecommunications Circuit Switch Utilizing Circular Buffers

IP.com Disclosure Number: IPCOM000122161D
Original Publication Date: 1991-Nov-01
Included in the Prior Art Database: 2005-Apr-04
Document File: 3 page(s) / 111K

Publishing Venue

IBM

Related People

Farrell, JK: AUTHOR [+6]

Abstract

This article describes a circuit arrangement that uses two circular buffers and array chaining to do switching between two layer 1 integrated services digital network (ISDN) bearer (B) channels.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Direct Memory Access-Based Integrated Services Digital Network Telecommunications
Circuit Switch Utilizing Circular Buffers

      This article describes a circuit arrangement that uses
two circular buffers and array chaining to do switching between two
layer 1 integrated services digital network (ISDN) bearer (B)
channels.

      A multi-port ISDN basic and/or primary rate communications
adapter can perform private branch exchange (PBX) like circuit
switching capabilities by using the circuit disclosed herein to
switch individual bearer channels from one ISDN port to another ISDN
port while continuing to process other bearer channels data as a
normal data communications terminal attachment.  This scheme can be
used to switch digitized voice as well as data although care must be
taken to minimize total delay in the path to preserve voice quality.

      The ISDN data link controller (IDLC) chip provides the open
systems interconnect (OSI) layer 2 high-level data link control
(HDLC) framing function for 32 channels which is sufficient to
support all 30 B + D or 23 B + D channels of North American
or European primary rate ISDN.  Each B (bearer) or D (delta) channel
operates at 64K bits per second (Kbps) on primary rate.  The IDLC can
also support HO, H10, H11, or H12 higher data rate channels.  The
IDLC also contains a full duplex direct memory access (DMA)
controller function for each channel supported.

      An integrated ISDN module (IIM) chip provides the OSI layer 1
function and the OSI layer 2 HDLC framing function for two ISDN basic
rate ports.  Each port has 2 B + D channels.  Each B (bearer) channel
operates at 64 Kbps on primary rate.  The basic rate D (delta)
channel operates at 16 Kbps.  The IIM also contains a full duplex DMA
controller function for each channel supported.

      Both the IDLC chip and the IIM chip have the ability to allow
any channel (or channels) to bypass the protocol processor mechanism
to provide a clear full duplex channel (or channels) between an ISDN
interface and the DMA controller to/from memory.  The DMA controller
for any channel of the IDLC or the IIM can be set up to transfer
received data into a...