Browse Prior Art Database

Multiple Valued Logic Multiplexer

IP.com Disclosure Number: IPCOM000122164D
Original Publication Date: 1991-Nov-01
Included in the Prior Art Database: 2005-Apr-04
Document File: 3 page(s) / 75K

Publishing Venue

IBM

Related People

Barcelo, P: AUTHOR [+3]

Abstract

This article describes a multiple valued logic (MVL) device that multiplexes several input lines into one output line.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Multiple Valued Logic Multiplexer

      This article describes a multiple valued logic (MVL)
device that multiplexes several input lines into one output line.

      MVL systems are logic systems in which the radix is > 2.  MVL
algebra, also known as Postian algebra, defines several logic
operators that can be implemented as gates for digital systems with a
radix > 2.  Postian algebra defines the following operators:
      A AND B = minimum value of A,B
      A OR B = maximum value of A,B
      A INVERT = N- 1 - A; N = radix of system
      A CYCLE B = (A + B) mod N

      These operators form the basis for MVL designing. Functional
expressions can be defined through the use of these operators in much
the same way as binary functions can be represented by Boolean
algebra.  Another operator used in this disclosure is the EQUAL
function gate.  This function is defined as shown in Fig. 1.

      Control signals in the MVL Multiplexer disclosed herein are
based on 0 through N - 1, where N = radix.  When a positive active
control signal is at N = 1, the signal is active.

      The MVL multiplexer presented herein is also known as an MVL
data selector.  The MVL multiplexer has a single select signal which
selects one of the N input lines.  Each level presented at the select
signal corresponds to each of the N input lines.

      The MVL multiplexer is illustrated in Fig. 2.  The MVL
multiplexer has one select line (SEL), N input lines, and one output
line...