Browse Prior Art Database

How to Handle Logical Device to Physical Scan String Location

IP.com Disclosure Number: IPCOM000122183D
Original Publication Date: 1991-Nov-01
Included in the Prior Art Database: 2005-Apr-04
Document File: 2 page(s) / 73K

Publishing Venue

IBM

Related People

Bordovsky, JS: AUTHOR [+4]

Abstract

Disclosed is a method to enable engineers to see chip LSSD scan string data in a familiar form and to be able to group data into logical devices in any arbitrary form for test purposes. The support processor is used as a debug tool by both hardware design engineers and software engineers. A support processor is a system of hardware and software taken together to form a single tool. Engineers using the support processor want to see their chips data in a familiar form: registers, latches and whatever devices they are used to. They even expect to be able to manipulate these devices using the same names they used when they designed the chips. Engineers might want to group together normally unrelated bits to be manipulated as a group, or pseudo device.

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This is the abbreviated version, containing approximately 52% of the total text.

How to Handle Logical Device to Physical Scan String Location

      Disclosed is a method to enable engineers to see chip
LSSD scan string data in a familiar form and to be able to group data
into logical devices in any arbitrary form for test purposes.  The
support processor is used as a debug tool by both hardware design
engineers and software engineers.  A support processor is a system of
hardware and software taken together to form a single tool. Engineers
using the support processor want to see their chips data in a
familiar form:  registers, latches and whatever devices they are used
to.  They even expect to be able to manipulate these devices using
the same names they used when they designed the chips.  Engineers
might want to group together normally unrelated bits to be
manipulated as a group, or pseudo device.  The data available to the
support processor is strictly a sequential set of bits coming from
several chips.  There is no such thing as a 'register' or 'latch' at
this level, only sequential bits from the zeroth bit to the Nth bit.
The bits of a single device, or register, as viewed by the engineer,
looks contiguous and might be 'numbered' from 0 to 31, which is a
relative numbering system.  However, the bits comprising the register
might be scattered all over the scan string, and in any order, and
might even be inverted.

      Please see the figure for the following details.  For each type
of chip in a machine, there will be one CHIPTYP-REC structure to
define t...