Browse Prior Art Database

Micro Channel I/O Buffer Card

IP.com Disclosure Number: IPCOM000122185D
Original Publication Date: 1991-Nov-01
Included in the Prior Art Database: 2005-Apr-04
Document File: 3 page(s) / 127K

Publishing Venue

IBM

Related People

Tarango, BA: AUTHOR

Abstract

Disclosed is a design for isolating feature cards from the host test system during manufacturing functional (AC equivalent) tests. This design allows for the plugging of circuit cards into a system, without dropping system power and without incurring damage to either the test system or the feature card under test.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 51% of the total text.

Micro Channel I/O Buffer Card

      Disclosed is a design for isolating feature cards from
the host test system during manufacturing functional (AC equivalent)
tests.  This design allows for the plugging of circuit cards into a
system, without dropping system power and without incurring damage to
either the test system or the feature card under test.

      Currently, functional testing of feature cards is performed by
placing a feature card into a system which is functionally equivalent
to the feature card's host system and exercising the various
functions of the feature card. The feature card is either placed into
the test system directly or through a 'pin-for-pin' extender card.
This method of testing provides virtually no protection to the test
system; serious hardware faults can migrate and damage the host
system.  Moreover, it is generally necessary to power down the system
to remove/ place the feature card into the system.  This increases
test cycle time, which decreases production efficiency.  A circuit
card design is presented which not only provides buffering to the
host test system, thereby reducing the possibility of fault
migration, but also circumvents the need to recycle power when
removing or inserting a feature card in the test system.

      A general design of the circuit card will be presented first.
The specifics of the MICRO CHANNEL* I/O Buffer Card will then be
discussed.  The general design of an I/O buffer card consists of
buffer circuitry which serves to isolate the card under test from the
host system.  Additionally, this circuitry provides protection to the
test system by reducing fault migration from the card under test. The
buffer card must allow for the removal of a feature card from the
host system, without triggering errors on the host system.  These
general requirements can be met as follows: First, a split power
plane can be incorporated to apply and remove power to the card under
test; this allows for voltage biasing the card under test without
affecting the host system's power.  Second, buffer circuitry must be
used to isolate all communication between the host system and the
card under test.  This circuitry must have very small propagation
delay (under 10 nsec.), relatively fast switching time (less than .1
msec.)  and have the capability to mask those lines which would cause
system errors due to the removing of the feature card from the host
system.  The flow of operation is shown in Fig. 1.

      Having determined what the general requirements for a feature
card are, the specific design of the MICRO CHANNEL I/O Buffer Card
can now be discussed. The MICRO CHANNEL I/O Buffer Card utilizes a
split power plane, isolating pow...