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Fast Array Test and Diagnosis

IP.com Disclosure Number: IPCOM000122192D
Original Publication Date: 1991-Nov-01
Included in the Prior Art Database: 2005-Apr-04
Document File: 3 page(s) / 117K

Publishing Venue

IBM

Related People

Savir, J: AUTHOR

Abstract

Disclosed is an array test scheme that has the following advantages: 1. It can be used in both built-in mode and off chip/module mode. 2. It can be used to test and diagnose both naked and embedded arrays. 3. Fault diagnosis is simple and is "free" during testing. 4. It is never subject to aliasing. 5. Depending on the test length, it can detect all kinds of failures, like stuck-cells, decoder faults, shorts, pattern-sensitive, etc. 6. If used as built-in feature, it does not slow down the array during normal operation. 7. It does not require storage of correct responses. A single response bit always indicates whether a fault has been detected. Thus, the storage requirement for the implementation of the test is zero. 8. If used as a built-in feature, the hardware overhead is very small.

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Fast Array Test and Diagnosis

      Disclosed is an array test scheme that has the following
advantages:
1.   It can be used in both built-in mode and off chip/module mode.
2.   It can be used to test and diagnose both naked and embedded
arrays.
3.   Fault diagnosis is simple and is "free" during testing.
4.   It is never subject to aliasing.
5.   Depending on the test length, it can detect all kinds of
failures, like stuck-cells, decoder faults, shorts,
pattern-sensitive, etc.
6.   If used as built-in feature, it does not slow down the array
during normal operation.
7.   It does not require storage of correct responses.  A single
response bit always indicates whether a fault has been detected.
Thus, the storage requirement for the implementation of the test is
zero.
8.   If used as a built-in feature, the hardware overhead is very
small.

      In the present scheme, the data to be stored inside the array
could be algorithmically generated, and if the same data can be
independently regenerated during the read-out time, then a simple
comparison circuitry can tell whether the word currently being read
is in error.  A miscompare at any given time will not only detect a
failure, but will also pinpoint to the affected address.  This is
basically the idea behind this disclosure.

      The method of test and diagnosis on a single-port naked array
is illustrated.  Embedded arrays may be treated similarly, except
that a one-to-one correspondence has to be established between
PIs/latches and address line before a read and write operation.
Multiport arrays can also be treated in a similar fashion.

      Figs. 1 and 2 are block diagrams of the hardware involved in
test mode. The single port array consists of N words of n bits each.
The decoder associated with the array has K inputs such that 2k/N.
The array is assumed to have a buffer that holds the contents of the
accessed word in read mode.  The buffer is not essential, though, and
the method will also apply when the array has no such buffer.  The
R/W line is the read/write control.  LFSR1 and LFSR2 are two
identical linear feedback shift registers implementing a primitive
polynomial of degree n. The comparator is shown in block diagram form
in Fig. 1, and in expanded form in Fig. 2.  The output of the
comparator indicates whether a fault has been detected at any time
during the test.  The inputs to the comparator are fed from the
buffer (Bi,i=1,2...,n) and from the stages of LFSR2 (Li,i=1,2,...,n).

      The test is conducted in the following way.  The R/W control is
set to write mode. The address space is stepped from 1 to N (address
stepper not shown in figures).

      LFSR1 and LFSR2 are seeded with the same non-zero seed (a...