Browse Prior Art Database

Common-Wordline Compact Merged DRAM Cell

IP.com Disclosure Number: IPCOM000122209D
Original Publication Date: 1991-Nov-01
Included in the Prior Art Database: 2005-Apr-04
Document File: 3 page(s) / 57K

Publishing Venue

IBM

Related People

Weinberg, ZA: AUTHOR

Abstract

Disclosed is a two-cell DRAM structure wherein both cells share a common gate, forming the wordline for two vertical FETs inside shallow trenches.

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Common-Wordline Compact Merged DRAM Cell

      Disclosed is a two-cell DRAM structure wherein both cells
share a common gate, forming the wordline for two vertical FETs
inside shallow trenches.

      Fig. 1 shows a cross-section of the cell.  Two FETs in a
vertical configuration share the same gate which forms the wordline.
The bitlines are buried inside the silicon wafer as N+ silicon rails.
The storage capacitors are connected to the top N+ sides of the FETs
as in the usual stack-capacitor DRAM.  Shallow trenches form the
isolation.

      Fig. 2 shows a possible top layout illustrating the main
features of the invention. The bitlines are entirely buried in the
substrate.  The wordline is formed of polysilicon which allows a
common gate formation to two vertical FETs. The wordline connects
adjacent cells by going up and clearing the contacts to the node
capacitors. The capacitors are formed on top as in the usual
stacked-capacitor cell.

      The advantage of this cell is in its compactness.

      Because the bitline is formed by a long rail of N+ silicon it
may look as if its RC time-constant is prohibitive.  However, Fig. 3
shows a sketch of the bitline dimensions, and the following estimated
calculation, for its resistance and capacitance, shows that the RC is
quite low.