Browse Prior Art Database

ECC Distributed Across Cache Line

IP.com Disclosure Number: IPCOM000122221D
Original Publication Date: 1991-Nov-01
Included in the Prior Art Database: 2005-Apr-04
Document File: 3 page(s) / 109K

Publishing Venue

IBM

Related People

Gilda, G: AUTHOR

Abstract

Disclosed below is a means of organizing a byte-sliced L2 cache design with ECC matrix, whereby the following advantages are achieved: 1. An 8-byte-wide ECC matrix can be implemented within 1 VLSI chip technology without degrading performance with chip crossings. 2. The critical timing path through the ECC matrix is only accessed one time per fetch and store operations for an L2 cache line rather than once per data transfer cycle between the L2 cache and source or destination of data.

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This is the abbreviated version, containing approximately 52% of the total text.

ECC Distributed Across Cache Line

      Disclosed below is a means of organizing a byte-sliced L2
cache design with ECC matrix, whereby the following advantages are
achieved:
      1.   An 8-byte-wide ECC matrix can be implemented within 1 VLSI
chip technology without degrading performance with chip crossings.
      2.   The critical timing path through the ECC matrix is only
accessed one time per fetch and store operations for an L2 cache line
rather than once per data transfer cycle between the L2 cache and
source or destination of data.

      The invention is implemented in a byte-slice L2 cache design
where data transfer between L2 cache and other system components is
on a logical doubleword basis.  A logical doubleword is that
doubleword addressed by S/370 real address bits 0 through 28.  There
are 8 VLSI chips, each containing a particular byte of all the
logical doublewords in the L2 cache.  Fig. 1 shows a simplified
organization of one of these chips.  An on-chip L2 cache array macro
1 is organized such that 8 bytes are read from the array on a read
cycle; each byte within the 8 bytes is associated with a different
logical doubleword in a 64-byte cache line.  The ordering of the
bytes is consecutive, i.e., byte 0 is the data byte x of logical
doubleword 0, byte 1 is byte x of logical doubleword 1, etc.  Eight
check bits are accessed along with the 8 bytes read from the array
macro to form the input to a SBEC/DBED ECC correction martix 2, and
these 8 check bits are associated with these 8 bytes.

      A bus between the L2 cache and an L1 cache allows for transfer
of one logical doubleword per cycle.  Each chip provides 1 of the 8
bytes needed to form the logical doubleword via an 8:1 multiplexer
and a 1 byte bus output register 3.  The 8-byte output of each chip's
ECC matrix is used on a byte-per-cycle basis until a 64-byte line has
been transferred.  The timing of a line fetch data transfer is shown
in Fig.2.  As mentioned before in (2) above, the ECC correction
matrix is only applied during the n cycle(s) in Fig. 2.  The data out
of the array is then held for the duration of the data transfer, and
the multiplexer determines which byte is provided to the bus output
register.  Thi...