Browse Prior Art Database

Variable Block Shift Delay Book

IP.com Disclosure Number: IPCOM000122234D
Original Publication Date: 1991-Nov-01
Included in the Prior Art Database: 2005-Apr-04
Document File: 2 page(s) / 78K

Publishing Venue

IBM

Related People

Braden, JJ: AUTHOR [+4]

Abstract

A circuit for supplying a variable amount of block shift delay to a data pulse is disclosed. The circuit shifts both edges of a data pulse by an amount determined by capacitance and current.

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This is the abbreviated version, containing approximately 52% of the total text.

Variable Block Shift Delay Book

      A circuit for supplying a variable amount of block shift
delay to a data pulse is disclosed.  The circuit shifts both edges of
a data pulse by an amount determined by capacitance and current.

      The variable block shift delay book incorporates a capacitive
discharge scheme twice in the same book.  This is done so that both
edges of the data pulse can be delayed the same variable amount.

      The schematic of this book is shown in the figure. This delay
book operates on differential signals only. Differential signals are
used to keep signal paths fast, provide immunity to noise, and to
ease the process of providing the block shift function.

      The differential pulse enters at the + and - IN pins and is
immediately emitter-followed by Q6 and Q7.  After Q6 and Q7 the
signal is sent to two different differential pairs.  The first
differential pair is Q8 and Q9 and the second differential pair is
Q15 and Q16.  The individual function of both these differential
pairs will be discussed next.

      Differential pair Q8 and Q9 are used to amplify the voltage
swing of the differential signal.  The amplified signal is
emitter-followed by Q10 and Q11 which drive two capacitors C0 and C1,
respectively.  Q10 and Q11 charge the capacitors very quickly but
allow the capacitors to discharge at a rate dependent on the current
in current sources ID.  Thus, the delay is achieved when the
capacitors discharge through a certain voltage.  The delay is
calculated as follows dT=C*dV/ID where:
         C  = Capacitance of C0=C1.
         ID = Current in each of the two identical current
              sources (ID).
         IE = (BIAS-Vbe)/1.0R
         dV = (R9+R10)*IE-R8*2*IE = IE*(R9+R10-(2*R8)) =
      ...