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Digitally Selectable Fixed Delay Circuit

IP.com Disclosure Number: IPCOM000122238D
Original Publication Date: 1991-Nov-01
Included in the Prior Art Database: 2005-Apr-04
Document File: 3 page(s) / 66K

Publishing Venue

IBM

Related People

Johnson, CL: AUTHOR [+3]

Abstract

Described is an on-chip means of generating additional reference edges from an input reference edge. The circuit described will function in a system where there is a requirement for supporting multiple system cycle times with the same level of hardware. Only one chip design is required to support multiple clock cycle times. The design allows for the optimization of a single critical path. The design requires no additional I/Os, and the delay can be selected at machine IPL by scanning the Digitally Selectable Fixed Delay (DSFD) control latches to the appropriate values. The circuit can be implemented in any technology and can be extended to support any number of system cycle time requirements.

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Digitally Selectable Fixed Delay Circuit

      Described is an on-chip means of generating additional
reference edges from an input reference edge.  The circuit described
will function in a system where there is a requirement for supporting
multiple system cycle times with the same level of hardware.  Only
one chip design is required to support multiple clock cycle times.
The design allows for the optimization of a single critical path.
The design requires no additional I/Os, and the delay can be selected
at machine IPL by scanning the Digitally Selectable Fixed Delay
(DSFD) control latches to the appropriate values.  The circuit can be
implemented in any technology and can be extended to support any
number of system cycle time requirements.

      The Digitally Selectable Fixed Delay circuit is made up of four
main sections (see Fig. 1):
     1.  The Primary/Secondary Delay Section
     2.  The Control Section
     3.  The Path Selector Section
     4.  The Repowering Section

      A primary delay is chosen to match the normal or most desired
clock cycle.  This primary delay would be optimized to give the best
tolerance possible to minimize clock skew. The secondary delays would
be used for alternate system cycle times (low tolerance/tight
designs) or for possible test and debug modes where a higher
tolerance, looser delay design could be utilized.

      The primary and secondary paths are selected under the control
of the scan lat...