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AC Interconnect Test With Series Boundary Scan

IP.com Disclosure Number: IPCOM000122240D
Original Publication Date: 1991-Nov-01
Included in the Prior Art Database: 2005-Apr-04
Document File: 6 page(s) / 258K

Publishing Venue

IBM

Related People

Graham, PK: AUTHOR

Abstract

Described is a boundary scan structure, associated control, and test pattern sequence by which safe, effective AC interconnect test can be done. The tests can be applied to any net or simultaneously to any group of nets for which test state initialization is not hindered by scan path adjacency of the SRLs of any two nets in the group.

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This is the abbreviated version, containing approximately 26% of the total text.

AC Interconnect Test With Series Boundary Scan

      Described is a boundary scan structure, associated
control, and test pattern sequence by which safe, effective AC
interconnect test can be done.  The tests can be applied to any net
or simultaneously to any group of nets for which test state
initialization is not hindered by scan path adjacency of the SRLs of
any two nets in the group.

      The focus of this AC testing is to trigger and capture driver
transitions between the two controlling states, 0 and 1.  It is
predicated on the existence and prior execution of a DC interconnect
test to ensure full test coverage and very defined failure diagnosis.
This scheme will work on any boundary structure in which the receiver
latch type (e.g., L2) is consistent for all boundary receivers and of
a different type than that of the driver and enable latches (e.g.,
L1), which is likewise consistent for all boundary drivers.

      The DC boundary scan structure used as reference herein is
described in [*].  The boundary latches are in series, i.e., in the
data paths, and are flushed in the functional mode by holding their
driver and receiver system clocks ON. There are two basic book
structures, one for common I/O and one for purely receiver inputs or
receiver fan out.

      In order to do AC interconnect testing as described herein, one
aspect of the DC boundary structure must be altered.  The driver data
L1 latch needs separate A clock control from the driver enable L1
latch.  Correspondingly, in the clock control logic, the A clock to
the enable latch and internal latches must be held off while the A
clock signal to the driver data L1 latches (and, optionally, to
receiver scan-only L1's) is pulsed during AC interconnect testing.
Lastly, the boundary latches must be ordered in the scan chain such
that the AC tests, which are dependent on the preceding latch to each
CIO boundary book, can be initialized.  This will be clarified below
after the test patterns are described.

      AC interconnect test will be described using the diagram in
Fig.  1, which represents two connected components.  Shown in the
component on the left is the controlling CIO book for this test along
with a preceding L2 (or potentially L2*) latch (P) in the chain and a
subsequent, additional fan-out receiver latch.  (The activity that
will be described for the preceding latch P would instead be that of
the scan- in pin were the boundary CIO latches actually the first in
the scan string.)

      Connected to the driver net under test in the component on the
right is another CIO book (Dn/En) and another fan-out receiver.  All
receiver latches participate in the test and are thus labeled R.  Dn
and En labels are used to indicate any number of driver books which
may be dotted onto the net and must all have their enable latches set
to 0 during the test of another source to the net.  The driver data
latch (Dn) states during the test are "don't car...