Browse Prior Art Database

Reconfigurable Signature Generator

IP.com Disclosure Number: IPCOM000122261D
Original Publication Date: 1991-Nov-01
Included in the Prior Art Database: 2005-Apr-04
Document File: 4 page(s) / 161K

Publishing Venue

IBM

Related People

Chan, GK: AUTHOR [+2]

Abstract

Disclosed is a method to increase the fault coverage of a Linear Feedback Shift Register (LFSR) signature generator without increasing the number of stages (registers) in the signature generator design. This new design will significantly reduce the hardware cost of a high fault-coverage LSFR signature generator.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 38% of the total text.

Reconfigurable Signature Generator

      Disclosed is a method to increase the fault coverage of a
Linear Feedback Shift Register (LFSR) signature generator without
increasing the number of stages (registers) in the signature
generator design.  This new design will significantly reduce the
hardware cost of a high fault-coverage LSFR signature generator.

      One of the methods to implement Functional-Self-Test (FST) or
Built-In-Self-Test (BIST) on the board level is signature analysis.
The basic idea is to capture serial data strings of card nets and
compress them into signatures. The self-test diagnostic software then
compares the captured signatures with the signatures of a known good
board and determines whether the nets being tested are good or
faulty.

      In general, the distribution of undetected errors (or fault
escapes) varies for different generator polynomials in a signature
generator, and all data compaction techniques lose some effective
fault coverage due to aliasing.  This is inevitable as long as the
length of the data bit stream is longer than the number of the
signature registers.  Since the lengths of the net data strings of
the FST or BIST may vary from a few bits to a few billion bits,
therefore, the fault escapes of the signature generator must be kept
to a minimum.

      Also, in applications such as BIST in circuit level, a
signature generator having a fixed generator polynominal may not be
desirable because a certain number of faults within the circuit may
never be detected for the particular generator polynomial, regardless
of the number of redundant tests taken.

      The degree of fault escapes is largely determined by the degree
of the generator polynomials, which are directly related to the
number of stages in its LSFR.  For example, the CRC-16 (16 stages)
has 2**(32-16) - 1 times the number of fault escapes as that of the
CRC-32 (32 stages).

      In a board test set-up, tens to a hundred of these signature
generators are required to test the board.  In order to reduce the
fault escapes, signature generators with longer stages are desirable.
However, since the hardware cost is directly proportional to the
number of stages in the signature generator design, trade-off must be
made to satisfy the fault-escape requirements while keeping the
hardware cost at an acceptable level.

      In this disclosure, we propose a solution to this problem:  the
Reconfigurable Signature Generator (RSG).  In applications where high
fault coverage is required, the LFSR signature generator is designed
such that different generator ploynomials can be selected.  Then
redundant tests with different generator polynomials are run, and
multiple signatures are generated and compared.

      The figure shows the general form of an n-stage RSG, and the
generator polynomial is defined as:
     G(X) = 1 + C1*X + C2* X**2 + ... + C(n-1)* X**(n-1) + Xn
where Ci, (1 < i <= n-1) is a binary multip...