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Syndrome Generator Test Mode for On-chip Error Correction Code

IP.com Disclosure Number: IPCOM000122315D
Original Publication Date: 1991-Nov-01
Included in the Prior Art Database: 2005-Apr-04
Document File: 1 page(s) / 37K

Publishing Venue

IBM

Related People

Fifield, JA: AUTHOR

Abstract

To test memory chips having on-chip error correction code (ECC) systems, a means is provided for testing the storage cells of both data bits and check bits wherein syndrome bits are observed directly as input tests are applied.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 100% of the total text.

Syndrome Generator Test Mode for On-chip Error Correction Code

      To test memory chips having on-chip error correction code (ECC)
systems, a means is provided for testing the storage cells of both
data bits and check bits wherein syndrome bits are observed directly
as input tests are applied.

      Referring to the figure, an ECC word bus 2 carrying data bits 4
and check bits 6 comes in to data corrector and syndrome generator
logic block 8.  Syndrome bus 10 terminates in logic 8.  Multiplexing
AND gates, e.g., A1, A2, A3, and A4 output check bits to off chip
drivers when control input IN to inverter I is high.  When IN is low,
syndrome outputs are sent out.  Output registers, decode and wiring
associated with check bit channels contained in box 12 can be used
twice, thereby reducing chip overhead and complexity.

      Proper test coverage of the syndrome logic circuits within
logic block 8 can be achieved by application of test vectors to ECC
word bus 2 and monitoring syndrome bits on bus 10 directly for
correct response.

      Disclosed anonymously.