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Browse Prior Art Database

High Efficiency N-Well Pump

IP.com Disclosure Number: IPCOM000122320D
Original Publication Date: 1991-Nov-01
Included in the Prior Art Database: 2005-Apr-04
Document File: 1 page(s) / 40K

Publishing Venue

IBM

Related People

Galbi, DE: AUTHOR [+2]

Abstract

By using low threshold NFET devices for pass devices, a two-stage pump circuit supplies more current and has one third less total pump capacitance than a conventional three-stage pump.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 100% of the total text.

High Efficiency N-Well Pump

      By using low threshold NFET devices for pass devices, a
two-stage pump circuit supplies more current and has one third less
total pump capacitance than a conventional three-stage pump.

      Referring to the figure, a two-stage pump is constructed using
three low threshold NFET devices L as unidirectional pass devices to
provide voltage at pad P about a volt above voltage supply VH.
Conventional three-stage pump circuits use four conventional NFETs as
pass devices but also have circuit elements: N-well inversion
capacitance NWIC, inverters I, and N-well capacitance NWC.

      Low threshold devices L are formed by eliminating the usual
P-well implants from these devices in a standard CMOS process.  Under
typical backgate voltage of -2.0 volts this substrate defined NFET
has a threshold voltage of approximately 300 millivolts, thereby
becoming a useful pass transistor.

      Even with sufficient channel length in pass devices L to make
barrier lowering non-critical, area of this new pump design is
significantly less than area of the conventional three-stage circuit.

      Disclosed anonymously.