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Browse Prior Art Database

BICMOS And-Or Invert with Short Fall Delay

IP.com Disclosure Number: IPCOM000122321D
Original Publication Date: 1991-Nov-01
Included in the Prior Art Database: 2005-Apr-04
Document File: 1 page(s) / 35K

Publishing Venue

IBM

Related People

Wissel, L: AUTHOR

Abstract

With each leg of an AND-OR-INVERT (AOI) circuit driving separate NPN transistors having a common collector tied to the output node, fast fall time is achieved.

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This is the abbreviated version, containing approximately 100% of the total text.

BICMOS And-Or Invert with Short Fall Delay

      With each leg of an AND-OR-INVERT (AOI) circuit driving
separate NPN transistors having a common collector tied to the output
node, fast fall time is achieved.

      As shown in the figure, NFET logic stack A comprised of
transistors A0, A1, and A2 drives the base of NPN transistor Q1 and a
logic stack B comprised of transistors B0, B1, and B2 drives the base
of NPN transistor Q2.  NPN collectors and conventional pull-up
circuits are connected to node OUT. Transistors T1 and T2 bleed
leakage current from stacks B and A, respectively, while node OUT is
high.  Inverter I and transistors T3 and T4 are "full swing finish"
elements which complete a falling transition all the way to ground
potential.

      Having all capacitance associated with stack A isolated from
capacitance of stack B results in a fast fall transition.

      Disclosed anonymously.