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Enhanced BiNMOS Circuit

IP.com Disclosure Number: IPCOM000122325D
Original Publication Date: 1991-Nov-01
Included in the Prior Art Database: 2005-Apr-04
Document File: 1 page(s) / 36K

Publishing Venue

IBM

Related People

Wissel, L: AUTHOR

Abstract

By buffering the gate of a very large NMOS pull-down transistor from a previous stage using an embedded emitter follower, area occupied by certain circuits, e.g., a two-input AND, is reduced while retaining performance of conventional full BiCMOS circuits.

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Enhanced BiNMOS Circuit

      By buffering the gate of a very large NMOS pull-down transistor
from a previous stage using an embedded emitter follower, area
occupied by certain circuits, e.g., a two-input AND, is reduced while
retaining performance of conventional full BiCMOS circuits.

      An enhanced BiNMOS, two-input AND circuit is shown in the
figure.  N-type transistor T0 is made sufficiently large to match the
pull-down characteristics of a conventional full BiCMOS circuit,
which has an NPN pull-down device.  The gate of transistor T0 is
driven by an embedded emitter follower comprised of transistors T1,
T2, and Q0.  Thus, the large gate capacitance of transistor T0 is
prevented from loading and slowing down the previous stage.

      Conventional portions of the circuit include inputs IN1 and IN2
to NAND A, inverter I, and P-type transistor T3.

      The BiNMOS portion of this circuit that has an associated
embedded emitter follower can be used extensively in BiCMOS logic
circuits resulting in significant density improvement with no
performance penalty.

      Disclosed anonymously.