Browse Prior Art Database

Technique for Forming Capacitors

IP.com Disclosure Number: IPCOM000122330D
Original Publication Date: 1991-Nov-01
Included in the Prior Art Database: 2005-Apr-04
Document File: 1 page(s) / 44K

Publishing Venue

IBM

Related People

Wilbarg, RR: AUTHOR

Abstract

The one-transistor memory cell relies on a capacitor for circuit performance. Current technology utilizes deep trenches and multilayer polysilicon winged structures to minimize the area required to form the capacitor.

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Technique for Forming Capacitors

      The one-transistor memory cell relies on a capacitor for
circuit performance.  Current technology utilizes deep trenches and
multilayer polysilicon winged structures to minimize the area
required to form the capacitor.

      The subject of this invention is a new technique for forming
capacitors for the one-transistor memory cell. Reactive ion etching
of silicon must typically be tuned and load adjusted to avoid etching
and causing "black silicon". The "black silicon" typically is
composed of dendrites formed by etching away the material between the
dendrites. By changing the loading and tuning conditions and by
regulating the time of the etch the dendrites can be varied in size
down to approximately 0.1 um in diameter.  The spacing between
dendrites can be varied to 0.1 um and the depth can be in excess of
10 times the diameter of the dendrite (<1 um).  Substrates of this
type have been built using both Chlorine and Sulphur based etchants
in Reactive Ion Etch systems.  The type and concentration of doping
in the silicon did not affect the formation of the structures.

      The capacitor is formed by growing a thin oxide on the dendrite
like Si structures (oxide thickness < 1/2 the dendrite thickness) and
then filling the structure with polysilicon.  Standard chem/mech
polishing can be used to level the surface.

      Contact to the top side of the capacitor is made using standard
metallurgical contact to polysi...